United Microelectronics Corp.

Primax Electronics Ltd.

Dell Products Inc.

Industrial Technology Research Institute

Egalax_empia Technology Inc.

Shih-Chieh Hsu

Chi-Horn Pai

Sheng-Yuan Hsueh

Pei-Ming Chang

Yi-Chung Sheng

Chih-Chiang Wu

Yao-Chang Wang

Wei-Lung Huang

Shyh-Fann Ting

Cheng-Tung Huang

Kuo-Hsing Lee

Chia-Fu Hsu

Chun-Mao Chiou

Chia-Chen Sun

Lung-En Kuo

Jian-Cun Ke

Ying-Hung Chou

Kun-Hsien Lee

Jie-Ning Yang

Shi-Jie Zhang

Zen-Jay Tsai

Chi-Sheng Tseng

Chang-Chien Wong

Ching-Hsiang Tseng

Pao-Chung Chao

Chun-Lung Chen

Meng-Yi Wu

Tzyy-Ming Cheng

Wen-Han Hung

Hsuan-Hsu Chen

Chih-Kai Kang

Li-Shian Jeng

Po-Kuang Hsieh

Shao-Hua Hsu

Po-Lun Cheng

Chun-Chia Chen

You-Di Jhang

Jing-Hui Lee

Shu-Hsuan Chih

Shih-Hao Su

Chu-Yin Tseng

Chun-Hsien Lin

Shih-Fang Tzou

Cheng-Chung Lee

Shui-Yen Lu

Yu-Yang Chang

Chia-Wen Liang

Po-Cheng Huang

Sheng-Hao Lin

Chiu-Hsien Yeh

Po-Jui Liao

Tsung-Hsun Wu

Chih-Chung Chen

Chang-Chi Huang

Hung-Yi Wu

Kun-Szu Tseng

Huang-Yi Lin

Ching-Hwa Tey

Duan-Quan Liao

Kuang-Hung Huang

Shih-Chang Chang

Yu-Han Chien

Chih-Ho Wang

Yi-Kun Chen

Jen-Hong Huang

Chin-Lan Chen

Chang Chien Wong

Ching Hsiang Tseng

Chung-Min Shih

Jiun-Hung Shen

A one-time programmable (OTP) memory cell includes a substrate having an active area surrounded by an isolation region. A divot is disposed between the active area and the isolation region. A transistor is disposed on the active area. A diffusion-contact fuse is electrically coupled to the transistor. The diffusion-contact fuse includes a diffusion region in the active area, a silicide layer on the diffusion region, and a contact partially landed on the silicide layer and partially landed on the isolation region. A sidewall surface of the diffusion region in the divot is covered by the silicide layer. The divot is filled with the contact.

One-time programmable memory cell

A one-time programmable memory structure including a substrate, a transistor, a capacitor, and an interconnect structure is provided. The transistor is located on the substrate. The capacitor includes a first electrode, a second electrode, and an insulating layer. The first electrode is disposed above the substrate. The second electrode is disposed on the first electrode. The first electrode is located between the second electrode and the substrate. The insulating layer is disposed between the first electrode and the second electrode. The interconnect structure is electrically connected between the transistor and the first electrode of the capacitor. The interconnect structure is electrically connected to the first electrode at a top surface of the first electrode.

One-time programmable memory structure

A computing system initialization system includes a BIOS processing system coupled to a computing device via a first I/O access connection, to a BIOS memory system via a second I/O access connection that is a relatively higher speed I/O access connection than the first I/O connection, and to a BIOS module. The BIOS processing system retrieves device data from the computing device via the first I/O access connection, stores the device data in the BIOS memory system via the second I/O access connection, and performs initialization operations subsequent to storing the device data in the BIOS memory system. During the initialization operations, the BIOS processing determines that the BIOS module requires the device data and, in response, retrieves the device data from the BIOS memory system via the second I/O access connection, and provides the device data that was retrieved from the BIOS memory system to the BIOS module.

Computing system initialization system

A one-time programmable (OTP) memory cell includes a substrate comprising an active area surrounded by an isolation region, a transistor disposed on the active area, and a diffusion-contact fuse electrically coupled to the transistor. The diffusion-contact fuse includes a diffusion region in the active area, a silicide layer on the diffusion region, and a contact partially landed on the silicide layer and partially landed on the isolation region.

One-time programmable memory cell and fabrication method thereof

A computing system initialization system includes a computing device that is coupled to a management device and that includes a processing system having at least one register storing debug-message-display-determination instructions, and a memory system that is coupled to the processing system and that includes Basic Input/Output System (BIOS) instructions that, when executed by the processing system, cause the processing system to provide a BIOS engine. The BIOS engine begins initialization operations and, during those initialization operations, generates at least one first debug message. The BIOS engine then accesses the at least one register included in the processing system to execute the debug-message-display-determination instructions and, in response, determines that the at least one first debug message should be displayed. In response, the BIOS engine transmits the at least one first debug message to the management device such that the management device displays the at least one first debug message.

Computer initialization debug message display system

The invention provides a semiconductor memory cell, the semiconductor memory cell includes a substrate having a first conductivity type, a doped region in the substrate, wherein the doped region has a second conductivity type, and the first conductivity type is complementary to the second conductivity type, a capacitor insulating layer and an upper electrode on the doped region, a transistor on the substrate, and a shallow trench isolation disposed between the transistor and the capacitor insulating layer, and the shallow trench isolation is disposed in the doped region.

Semiconductor memory cell and the forming method thereof

A wireless sound output device includes a wireless earbud and a charging base. The wireless earbud is placed in the charging base. If a true wireless stereo Bluetooth controller of the wireless earbud detects that a mode switching circuit of the charging base is switched to a wireless Bluetooth receiver mode, an analog signal is transmitted to an audio source output hole of the charging base through an audio source analog signal output switching unit of the wireless earbud.

Wireless sound output device with charging function

A method for communicating with an under-test object and a communicating system are provided. The method includes the following steps. A command signal is provided from a processing unit of the communicating system to the under-test object, and the processing unit waits for receiving a response signal from the under-test object. If the response signal from the under-test objecthas not been received by the processing unit for a predetermined waiting time period, the command signal is provided to the under-test object again and the predetermined waiting time period is adjusted. There is an exponential relation between the predetermined waiting time period and the number of times the command signal is provided to the under-test object.

Communicating method and communicating system

A camera module testing method is applied to a camera module including a camera lens and a photosensitive element. In a step (A), an original image is captured through the camera lens and the photosensitive element. In a step (B), the original image is converted into a gray scale image. In a step (C), the gray scale image is converted into a binary image according to a critical gray scale value. In a step (D), a boundary contour is obtained according to plural pixels of the binary image higher than or equal to the critical gray scale value. In a step (E), a contour center of the boundary contour is obtained. Then, a step (F) is performed to judge whether an optical axis of the camera lens is aligned with an imaging center of the photosensitive element according to the imaging center and the contour center.

Camera module testing method

An information management method for a testing network framework is provided. The testing network framework includes a first server and at least one computer. The method includes the following steps. Firstly, the at least one computer downloads and executes a test application program. Then, the at least one computer is connected to the first server, and provides a device identification code and a network address value of the at least one computer to the first server. If the first server judges that the corresponding device identification code complies with a first default condition and the corresponding network address value complies with a second default condition, the corresponding computer is authenticated, and a test setting information is provided from the first server to the corresponding computer. After the test setting information is downloaded to the corresponding computer, a test process is performed.

Testing network framework and information management method applied thereto

An electronic device test system and method detects a memory serial number of an electronic device. The electronic device test system includes a Macintosh system computer, configured to execute a serial number detection program to detect the memory serial number of the electronic device; and a Windows system computer, configured to execute a serial number comparison program to compare whether the memory serial number of the electronic device satisfies a coding rule. The Macintosh system computer transmits the memory serial number to the Windows system computer by means of an RS232 interface for printing.

Electronic device test system and method thereof

An electronic device test system is configured to test functions of an electronic device. The electronic device test system includes: a test computer, configured to execute an electronic device test program; a scanning device, configured to scan a barcode number of the electronic device; and an optical sensor module, configured to detect a connection status of the electronic device and the test computer. When the optical sensor module confirms the connection status, the electronic device test program starts a test function to test the electronic device, records a test result of the electronic device according to the barcode number, and subsequently generates a retest rate according to the test result.

A semiconductor device includes an interfacial layer on a substrate and agate structure on the interfacial layer. Preferably, the gate structure includes a patterned high-k dielectric layer, the patterned high-k dielectric layer comprises a metal oxide layer, and a horizontal direction width of the patterned high-k dielectric layer and a horizontal direction width of the interfacial layer are different. The semiconductor device also includes a first spacer adjacent to the gate structure and on part of the interfacial layer and contacting a top surface of the interfacial layer and a second spacer on the sidewalls of the first spacer and the interfacial layer. Preferably, a planar bottom surface of the second spacer is lower than a planar bottom surface of the first spacer and extending along a same direction as the planar bottom surface of the first spacer.

Semiconductor device and method for fabricating the same

A testing system uses different operating systems to test electronic products. The testing system includes a master computer, a slave computer and a relay. A first operating system is installed in the master computer. A second operating system is installed in the slave computer. The master computer and the slave computer are connected with each other through RS-232 ports. The relay is connected with the master computer, the slave computer and an under-test product. By changing the voltage level state of specified pins of the RS-232 ports, the master computer notifies the slave computer to test the under-test product. Moreover, by controlling the relay, the connection between the master computer and the under-test product is switched to the connection between the slave computer and the under-test product. Consequently, the under-test product is tested by the slave computer.

Testing system using different operating systems to test electronic products

A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming an interfacial layer on the substrate; forming a stack structure on the interfacial layer; patterning the stack structure to form a gate structure on the interfacial layer; forming a liner on the interfacial layer and the gate structure; and removing part of the liner and part of the interfacial layer for forming a spacer.

Growing community of inventors

Taipei, Taiwan

Shih-Chieh Hsu