Taiwan Semiconductor Manufacturing Comp. Ltd.

Industrial Technology Research Institute

Tsinghua University

Genesys Logic, Inc.

Chung Yuan Christian University

Parabellum Strategic Oppurtunities Fund LLC

Shih-Chieh Chang

Shahaji B More

Cheng-Han Lee

Zheng-Yang Pan

Huai-Tei Yang

Chun-Chieh Wang

Yi-Min Huang

Ying-Lang Wang

Chih-Yu Ma

Kei-Wei Chen

Shu Kuan

Hsiu-Ting Chen

Cheng-Yi Peng

Kuo-Feng Yu

Yu-Ting Lin

Ting-Chang Chang

Chien Lin

Yi-Ming Huang

Yueh-Ching Pai

Chin-I Liao

Jian-Shin Tsai

Chih-Chang Huang

Ing-Ju Lee

Chun Hsiung Tsai

Szu-An Wu

Jun-Nan Nian

Ying-Min Chou

Ching-Yao Sun

Jyun-Ru Wu

Ching-Che Huang

Tsung-Lin Lee

Chun-Hsiung Tsai

Yu-Ku Lin

Chiang-Ming Chuang

Fu-Yen Jian

Chun Che Huang

Shiu-Ko JangJian

Pei-Ren Jeng

Chee-Wee Liu

Yu-Sheng Wang

Shyh-Shyuan Sheu

Chia-Hui Lin

Jung-Chih Tsao

Chun-Chang Chen

Shih-Wen Huang

Shih-Ho Lin

Shin-Yeu Tsai

Chih-Chung Chang

Kun-Yu Lee

Chung-En Tsai

Kuan-Chang Chang

Chih-Hung Pan

Tsung-Ming Tsai

Te-Ming Kung

Chien-Chih Lin

Chun Chieh Wang

Yong-En Syu

Li-Yen Fang

Hong-Hsien Ke

Fu-Cheng Tsai

Shih-Ya Lin

Yun-Wen Chu

Chiao-Ling Lung

Hsing-Chi Chen

Wen-Fu Tsai

Chun-Ju Huang

Shih-Hsien Cheng

Pei-Shan Lee

Chi-Cherng Jeng

Chii-Ming M Wu

Chi-Cheng Hung

Chandrashekhar Prakash Savant

Chien-Wei Lee

Chih-Sheng Lin

Wei-Jen Lo

Chien-Feng Lin

Wen-Chu Hsiao

Ching-Lun Lai

Sih-Han Li

Jian-Wei Su

Shih-Hsu Huang

Tay-Jyi Lin

Yow-Tyng Nieh

Yi-Ching Kuo

Yiyu Shi

Mon-Nan How

Chung-Han Chou

Jui-Hung Chien

Hao Yu

Ruei-Siang Hsu

Hsueh-Ju Lin

Yu-Shih Su

Chih-Hao Dai

Wen-Hung Lo

Yu-Te Hung

Chih Yung Hung

The present disclosure describes a method to form silicon germanium (SiGe) source/drain epitaxial stacks with a boron doping profile and a germanium concentration that can induce external stress to a fully strained SiGe channel. The method includes forming one or more gate structures over a fin, where the fin includes a fin height, a first sidewall, and a second sidewall opposite to the first sidewall. The method also includes forming a first spacer on the first sidewall of the fin and a second spacer on the second sidewall of the fin; etching the fin to reduce the fin height between the one or more gate structures; and etching the first spacer and the second spacer between the one or more gate structures so that the etched first spacer is shorter than the etched second spacer and the first and second etched spacers are shorter than the etched fin. The method further includes forming an epitaxial stack on the etched fin between the one or more gate structures.

Method of forming source/drain epitaxial stacks

A device includes a fin extending from a substrate, a gate stack over and along sidewalls of the fin, a gate spacer along a sidewall of the gate stack, and an epitaxial source/drain region in the fin and adjacent the gate spacer. The epitaxial source/drain region includes a first epitaxial layer on the fin, the first epitaxial layer including silicon, germanium, and arsenic, and a second epitaxial layer on the first epitaxial layer, the second epitaxial layer including silicon and phosphorus, the first epitaxial layer separating the second epitaxial layer from the fin. The epitaxial source/drain region further includes a third epitaxial layer on the second epitaxial layer, the third epitaxial layer including silicon, germanium, and phosphorus.

Semiconductor device and methods of forming same

A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a gate structure formed over a fin structure, and a gate spacer layer formed on a sidewall surface of the gate structure. The semiconductor structure includes a source/drain (S/D) epitaxial layer formed adjacent to the gate structure, and a dielectric spacer layer formed on the S/D epitaxial layer. The semiconductor structure includes a contact plug barrier formed over the S/D epitaxial layer, and a contact plug surrounding by the contact plug barrier, wherein the contact plug is separated from the gate spacer layer by the dielectric spacer layer and the contact plug barrier.

Semiconductor structure with source/drain multi-layer structure and method for forming the same

A method includes forming a first fin and a second fin over a substrate, depositing an isolation material surrounding the first and second fins, forming a gate structure along sidewalls and over upper surfaces of the first and second fins, recessing the first and second fins outside of the gate structure to form a first recess in the first fin and a second recess in the second fin, epitaxially growing a first source/drain material protruding from the first and second recesses, and epitaxially growing a second source/drain material on the first source/drain material, wherein the second source/drain material grows at a slower rate on outermost surfaces of opposite ends of the first source/drain material than on surfaces of the first source/drain material between the opposite ends of the first source/drain material, and wherein the second source/drain material has a higher doping concentration than the first source/drain material.

FinFET structures and methods of forming the same

A structure includes a stepped crystalline substrate that includes an upper step, a lower step, and a step rise. A first fin includes a crystalline structure having a first lattice constant. The first fin is formed over the lower step. A second fin includes a crystalline structure having a second lattice constant, the second lattice constant being different than the first lattice constant. The second fin can be formed over the upper step apart from the first fin. A second crystalline structure can be formed over the first crystalline structure and the tops of the fins aligned. The first and second fins can be made of the same material, but with different heights and different channel strain values. The first fin can be used as an NMOS fin and the second fin can be used as a PMOS fin of a CMOS FinFET.

FinFET EPI channels having different heights on a stepped substrate

A device includes a first gate region having a first gate length; a first spacer on a sidewall of the first gate region; a semiconductor layer over the first gate region; a second gate region over the semiconductor layer, wherein the second gate region has a second gate length equal to the first gate length; and a second spacer on a sidewall of second gate region, wherein the second spacer is wider than the first spacer.

Methods of forming gate structures with uniform gate length

An apparatus and a method for neural network computation are provided. The apparatus for neural network computation includes a first neuron circuit and a second neuron circuit. The first neuron circuit is configured to execute a neural network computation of at least one computing layer with a fixed feature pattern in a neural network algorithm. The second neuron circuit is configured to execute the neural network computation of at least one computing layer with an unfixed feature pattern in the neural network algorithm. The performance of the first neuron circuit is greater than that of the second neuron circuit.

Apparatus and method for neural network computation

A data feature augmentation system and method for a low-precision neural network are provided. The data feature augmentation system includes a first time difference unit. The first time difference unit includes a first sample-and-hold circuit and a subtractor. The first sample-and-hold circuit is used for receiving an input signal and obtaining a first signal according to the input signal. The first signal is related to a first leakage rate of the first sample-and-hold circuit and the first signal is the signal generated by delaying the input signal by one time unit. The subtractor is used for performing subtraction on the input signal and the first signal to obtain a time difference signal. The input signal and the time difference signal are inputted to the low-precision neural network.

Data feature augmentation system and method for low-precision neural network

A semiconductor device includes a substrate; a fin protruding above the substrate, the fin including a compound semiconductor material that includes a semiconductor material and a first dopant, the first dopant having a different lattice constant than the semiconductor material, where a concentration of the first dopant in the fin changes along a first direction from an upper surface of the fin toward the substrate; a gate structure over the fin; a channel region in the fin and directly under the gate structure; and source/drain regions on opposing sides of the gate structure, the source/drain regions including a second dopant, where a concentration of the second dopant at a first location within the channel region is higher than that at a second location within the channel region, where the concentration of the first dopant at the first location is lower than that at the second location.

FinFET device and methods of forming the same

A FinFET device and a method of forming the same are provided. The method includes forming semiconductor strips over a substrate. Isolation regions are formed over the substrate and between adjacent semiconductor strips. A first recess process is performed on the isolation regions to expose first portions of the semiconductor strips. The first portions of the semiconductor strips are reshaped to form reshaped first portions of the semiconductor strips. A second recess process is performed on the isolation regions to expose second portions of the semiconductor strips below the reshaped first portions of the semiconductor strips. The second portions of the semiconductor strips are reshaped to form reshaped second portions of the semiconductor strips. The reshaped first portions of the semiconductor strips and the reshaped second portions of the semiconductor strips form fins. The fins extend away from topmost surfaces of the isolation regions.

FinFET device and method of forming same

A method for forming a semiconductor device includes patterning a substrate to form a strip including a first semiconductor material, forming an isolation region along a sidewall of the strip, an upper portion of the strip extending above the isolation region, forming a dummy structure along sidewalls and a top surface of the upper portion of the strip, performing a first etching process on an exposed portion of the upper portion of the strip to form a first recess, the exposed portion of the strip being exposed by the dummy structure, after performing the first etching process, reshaping the first recess to have a V-shaped bottom surface using a second etching process, wherein the second etching process is selective to first crystalline planes having a first orientation relative to second crystalline planes having a second orientation, and epitaxially growing a source/drain region in the reshaped first recess.

The present disclosure describes a semiconductor device includes a substrate, a buffer layer on the substrate, and a stacked fin structure on the buffer layer. The buffer layer can include germanium, and the stacked fin structure can include a semiconductor layer with germanium and tin. The semiconductor device further includes a gate structure wrapped around a portion of the semiconductor layer and an epitaxial structure on the buffer layer and in contact with the semiconductor layer. The epitaxial structure includes germanium and tin.

Germanium tin gate-all-around device

In a method of manufacturing a semiconductor device, a fin structure in which first semiconductor layers and second semiconductor layers are alternately stacked is formed, a sacrificial gate structure is formed over the fin structure, a source/drain region of the fin structure, which is not covered by the sacrificial gate structure, is etched, thereby forming a source/drain space, the first semiconductor layers are laterally etched through the source/drain space, and a source/drain epitaxial layer is formed in the source/drain space. An inner spacer made of a dielectric material is formed on an end of each of the etched first semiconductor layers and at least one of the spacer has width changes along vertical direction of device. At least one of the first semiconductor layers has a composition different from another of the first semiconductor layers.

Method of manufacturing a semiconductor device and a semiconductor device

A semiconductor structure includes a substrate, a semiconductor fin extending from the substrate, and a silicon germanium (SiGe) epitaxial feature disposed over the semiconductor fin. A gallium-implanted layer is disposed over a top surface of the SiGe epitaxial feature, and a silicide feature is disposed over and in contact with the gallium-implanted layer.

Method for forming source/drain contacts

A semiconductor device includes semiconductor wires or sheets disposed over a substrate, a source/drain epitaxial layer in contact with the semiconductor wires or sheets, a gate dielectric layer disposed on and wrapping around each channel region of the semiconductor wires or sheets, a gate electrode layer disposed on the gate dielectric layer and wrapping around each channel region, and insulating spacers disposed in spaces, respectively. The spaces are defined by adjacent semiconductor wires or sheets, the gate electrode layer and the source/drain region. The source/drain epitaxial layer includes multiple doped SiGe layers having different Ge contents and at least one of the source/drain epitaxial layers is non-doped SiGe or Si.

Growing community of inventors

Taipei, Taiwan

Shih-Chieh Chang