Mediatek Corporation

National Yang Ming Chiao Tung University

Mediatek Singapore Pte. Ltd.

Shih-Chi Shen

Chun-Ming Kuo

Chii-Horng Chen

Chi-Hsueh Wang

Ho-Chi Huang

Shao-Wei Feng

YingYing Chen

JengYi Tsai

Hsin-Hung Chen

Ang-Sheng Lin

Ping-Hung Chiang

Wen-Rong Wu

Yen-Hui Yeh

Wen-Chang Lee

Xiaochuan Guo

Sheng-Hua Yang

Chieh-Hsun Hsiao

Ai-Hsuan Liu

Tso-Mo Chen

Yen-Ping Lin

In an aspect of the disclosure, a method, a computer-readable medium, and an apparatus are provided. The apparatus may be a UE. The configuration specifies a bundle size N. Modulation symbols in N consecutive PRBs are precoded with a same precoder. The UE determines whether a precoding condition is true. The precoding condition is that modulation symbols in a first set of resources and a second set of resources are precoded with a same precoder. Each set of the first set of resources and the second set of resources contains N PRBs. When the precoding condition is met: the UE measures reference signals in the second set of resources; the UE determines a channel condition of the first set of resources in consideration of the measurements of the reference signals in the second set of resources.

Inter-bundle channel estimation and synchronization for downlink data reception

The invention provides method and associated signal system improving mitigation of injection-pulling effect for an oscillator which generates an output clock under control of a control signal. The method may include: by a loop filter, filtering a deviation signal to form a filtered signal; by a SIL (self-injection locked) controller, forming an auxiliary signal which tracks the deviation signal or a phase difference between a reference clock and an output signal resulting from the output clock; and, forming the control signal by summing the filtered signal and the auxiliary signal.

Method and associated signal system improving mitigation of injection-pulling effect

A frequency-generating circuit includes a frequency synthesizer circuit and a controller. The frequency synthesizer circuit generates a radio-frequency clock signal according to a reference clock signal and a channel number. The controller is coupled to the frequency synthesizer circuit, generates a power-down control signal for controlling at least a portion of the frequency synthesizer circuit to power down. The frequency synthesizer circuit includes an accumulator for generating an accumulated value according to the channel number. The frequency synthesizer circuit generates the radio-frequency clock signal according to the reference clock signal and the accumulated value. The controller maintains the accumulated value of the accumulator when the portion of the frequency synthesizer circuit powers down.

Methods for controlling a frequency synthesizer circuit and a frequency-generating circuit utilizing the same

A frequency-generating circuit includes a frequency synthesizer circuit and a reference clock signal processor. The frequency synthesizer circuit receives a processed reference clock signal and generates a radio-frequency clock signal according to the processed reference clock signal. The reference clock signal processor receives an original reference clock signal from an oscillator and processes the original reference clock signal according to an indication signal to generate the processed reference clock signal. The indication signal is generated according to a required reference clock frequency of a communications apparatus. When the required reference clock frequency is high, a frequency of the processed reference clock signal is a multiple of a frequency of the original reference clock signal, and when the required reference clock frequency is low, the frequency of the original reference clock signal is a multiple of the frequency of the processed reference clock signal.

Frequency-generating circuit and communications apparatus

A frequency synthesizer includes a phase-locked loop (PLL) and a loop bandwidth controller. The PLL generates an output clock according to a reference clock. The loop bandwidth controller checks at least one indicator indicative of injection pulling/pushing of the PLL to configure a loop bandwidth of the PLL. In one exemplary design, the loop bandwidth controller sets the loop bandwidth of the PLL by controlling a configuration of a loop filter included in the PLL. For example, the PLL is an all-digital phase-locked loop (ADPLL), and the loop filter is a digital loop filter of the ADPLL.

Frequency synthesizer with injection pulling/pushing suppression/mitigation and related frequency synthesizing method thereof

A frequency synthesizer includes a digitally controlled oscillator, a sigma-delta modulation circuit and a controller. The digitally controlled oscillator is arranged to generate an oscillating clock. The sigma-delta modulation circuit is arranged to generate an SDM input to the digitally controlled oscillator. The controller is arranged to adjust an operating frequency of the SDM circuit in response to a transmit power level of a transmitter using the oscillating clock.

Frequency synthesizer and related method for improving power efficiency

A digitally-controlled oscillator (DCO) includes a first capacitor array and a second capacitor array responsive to an integer part and a fractional part of a digital control word, respectively. The mismatch measurement of the DCO includes a first settling phase and a second settling phase. In the first settling phase, the first capacitor array is fixed to have one capacitive value, and the second capacitor array is adjusted for making the DCO frequency locked to a target value. In the second settling phase, the first capacitor array is fixed to have another capacitive value, and the second capacitor array is adjusted for making the DCO frequency locked to the same target value. The capacitor mismatches are estimated according to characteristic values derived from the digital control word adaptively adjusted in the first setting phase and the second setting phase.

Method and apparatus for measuring/compensating mismatches in digitally-controlled oscillator

The invention provides a method for frequency offset estimation according to a filtered signal with destroyed phase information. In one embodiment, a filter filters an original signal according to a series of first filter coefficients to obtain a first-channel component of the filtered signal, and filters the original signal according to a series of second filter coefficients to obtain a second-channel component of the filtered signal. A series of third filter coefficients are first derived from the first filter coefficients. The original signal is then filtered according to the third filter coefficients to obtain a reference signal. A first frequency offset value is estimated according to the first-channel component of the filtered signal and the reference signal, wherein the first-channel component of the filtered signal is a first-channel component of an artificial signal, and the reference signal is a second-channel component of the artificial signal.

Method for frequency offset estimation and automatic frequency control for filtered signal with destroyed phase information and signal transceiver

A MIMO OFDM system for TICM includes a tone-level interleaver at the transmitter using a block of Nsymbols as its basic unit. This results in different decoding architectures at the receiver. The main advantage of TICM is to merge soft-bit demapping into the Viterbi algorithm. Taking advantage of the trellis structure inherent in the Viterbi algorithm, TICM can have lower computational complexity and potentially better performance than BICM with the LSD detector and the vector demapper. Although the tone-level interleaving may not have spatial diversity gain, the performance is not affected in 802.11n environments.

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Taipei, Taiwan

Shih-Chi Shen