Taiwan Semiconductor Manufacturing Comp. Ltd.

Shih-Chi Lin

Ying-Lang Wang

Yen-Ming Chen

Szu-An Wu

You-Hua Chou

Wen-Long Lee

Chi-Wen Liu

Chia-Ming Tsai

Yu-Hung Lin

Hon-Lin Huang

Yi-Lung Cheng

Chen-Ming Huang

Chandrashekhar Prakash Savant

Chyi-Tsong Ni

Chih-Tsung Lee

Tien-Wei Yu

Ming-Te Chen

Min Hao Hong

Chih-Jen Wu

Wen-Kung Cheng

Soon-Kang Huang

Chih-Yuan Yang

Kun-Tai Wu

Jun Wu

Jiann-Kwang Wang

Juin-Jie Chang

Zack Chong

Chin-Hsiang Chang

Ming-Hua Yoo

Wei-Jung Lin

Chia-Lin Hsu

Kuei-Wu Huang

Mei-Hui Fu

Francis Wang

Chen-Hua Douglas Yu

Chung-Shi Liu

Shau-Lin Shue

Kei-Wei Chen

Shiu-Ko JangJian

Ming-Hua Yu

Yung-Lung Hsu

Hsi-Kuei Cheng

Sheng-Hsuan Lin

Jung-Chih Tsao

Yu-Ku Lin

Yu-Min Chang

Yao-Hsiang Liang

Ching-Fu Yeh

Rueijer Lin

Hung-Chih Wang

Guang-Cheng Wang

Ke-Chih Liu

Ray Chuang

Ming-Hwa Yoo

Wei-Jen Liu

Hui-Hua Chang

Fu-Jier Fahn

Ying Lang Wang

Ming-Jer Lee

Jenq-Dong Sheu

Sez-An Wu

Guey-Bao Huang

Kuo-Chou Liu

Hui-ju Yu

Hsin-Chen Tsai

Hsin-Kai Chen

Dong-Xuan Lu

Yi-An Jian

Shien-Ping Feng

Chun Chun Yeh

Guey Bao Huang

Chih Chung Lee

Yali Tai

The present disclosure describes a method for forming gate stack layers with a fluorine concentration up to about 35 at. %. The method includes forming dielectric stack, barrier layer and soaking the dielectric stack and/or barrier layer in a fluorine-based gas. The method further includes depositing one or more work function layers on the high-k dielectric layer, and soaking at least one of the one or more work function layers in the fluorine-based gas. The method also includes optional fluorine drive in annealing process, together with sacrificial blocking layer to avoid fluorine out diffusion and loss into atmosphere.

Gate stack treatment

A method of using a polishing system includes securing a wafer to a support, wherein the wafer has a first diameter. The method further includes polishing the wafer using a first polishing pad rotating about a first axis, wherein the first polishing pad has a second diameter greater than the first diameter. The method further includes rotating the support about a second axis perpendicular to the first axis after polishing the wafer using the first polishing pad. The method further includes polishing the wafer using a second polishing pad after rotating the support, wherein the second polishing pad has a third diameter less than the first diameter. The method further includes releasing the wafer from the support following polishing the wafer using the second polishing pad.

Method of using a polishing system

A semiconductor structure and a method for forming the same are provided. The method for manufacturing a semiconductor structure includes forming a gate structure over a substrate and forming a spacer on a sidewall of the gate structure. The method for manufacturing a semiconductor structure further includes forming a hard mask structure on a top surface of the gate structure and on an upper portion of the spacer but not on a bottom portion of the spacer.

Gate structure with insulating structure and method for manufacturing the same

A polishing system includes a wafer support that holds a wafer, the wafer having a first diameter. The polishing system further includes a first polishing pad that polishes a first region of the wafer, the first polishing pad having a second diameter greater than the first diameter. The polishing system further includes an auxiliary polishing system comprising at least one second polishing pad that polishes a second region of the wafer, wherein the second polishing pad has a third diameter less than the first diameter, and the wafer support is configured to support the wafer during use of the first polishing pad and the auxiliary polishing system.

Polishing system

An improved interconnect structure and a method for forming the interconnect structure is disclosed that allows the interconnect structure to achieve a lower Rc. To lower the Rc of the interconnect structure, an &#x3b1;-phase inducing metal layer is introduced on a first Ta barrier layer of &#x3b2; phase to induce the subsequent deposition of Ta thereon into the formation of an &#x3b1;-phase Ta barrier layer. The subsequently deposited Ta barrier layer with a primary crystallographic structure of &#x3b1; phase has a lower Rc than that of the &#x3b2;-phase Ta barrier layer.

Method for forming interconnect structure

A polishing system for polishing a semiconductor wafer includes a wafer support for holding the semiconductor wafer, and a first polishing pad for polishing a region of the semiconductor wafer. The semiconductor wafer has a first diameter, and the first polishing pad has a second diameter shorter than the first diameter.

Polishing system and polishing method

A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate. The semiconductor device structure includes a gate stack positioned over the semiconductor substrate. The gate stack includes a gate dielectric layer and a gate electrode over the gate dielectric layer. The semiconductor device structure includes spacers positioned over first sidewalls of the gate stack. The spacers and the gate stack surround a recess. The semiconductor device structure includes an insulating layer formed over the semiconductor substrate and surrounding the gate stack. The semiconductor device structure includes a cap layer covering the insulating layer, the spacers, and inner walls of the recess.

Semiconductor device structure and method for forming the same

An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a contact layer over a substrate, a dielectric layer over the contact layer, a silicide layer over the exposed portion of the contact layer, a barrier layer along sidewalls of the opening, an alloy layer over the barrier layer, a glue layer over the alloy layer, and a conductive plug over the glue layer, wherein the dielectric layer has an opening, and the opening exposes a portion of the contact layer.

Interconnect structure and method of forming the same

An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a contact layer over a substrate; a dielectric layer over the contact layer, wherein the dielectric layer has an opening, the opening exposing a portion of the contact layer; a silicide layer over the exposed portion of the contact layer; a barrier layer along sidewalls of the opening; an alloy layer over the barrier layer; a glue layer over the alloy layer; and a conductive plug over the glue layer.

A semiconductor baking apparatus includes a load lock chamber, a process chamber, a transfer chamber, a first interior door, and a controller. The process chamber has a first accommodating space therein. The transfer chamber has a second accommodating space therein, and the transfer chamber is connected to the load lock chamber and the process chamber. The first interior door is between the process chamber and the transfer chamber. When the first interior door is opened, the first accommodating space is communicated with the second accommodating space. The controller is programmed to open the first interior door when the semiconductor baking apparatus idles.

Semiconductor baking apparatus and operation method thereof

A method of fabricating a copper interconnect on a substrate is disclosed in which the interconnect and substrate are subjected to a low temperature anneal subsequent to polarization of the interconnect and prior to deposition of an overlying dielectric layer. The low temperature anneal inhibits the formation of hillocks in the copper material during subsequent high temperature deposition of the dielectric layer. Hillocks can protrude through passivation layer, thus causing shorts within the connections of the semiconductor devices formed on the substrate. In one example, the interconnect and substrate are annealed at a temperature of about 200&#xb0; C. for a period of about 180 seconds in a forming gas environment comprising hydrogen (5 parts per hundred) and nitrogen (95 parts per hundred).

Low temperature method for minimizing copper hillock defects

A method of smoothening a dielectric layer. First, a substrate is provided. Next, a dielectric layer is formed on the semiconductor substrate. Finally, the dielectric layer is smoothened by a plasma treatment employing a silane based gas and a nitrogen based gas.

Method of smoothening dielectric layer

A method for spin-on wafer cleaning. The method comprises controlling spin speed and vertical water jet pressure. The vertical jet pressure and the spin speed are substantially maintained in inverse proportion. Wafer spin speed is between 50 to 1200 rpm. Vertical wafer jet pressure is between 0.05 to 100 KPa.

Methods of spin-on wafer cleaning

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Taipei, Taiwan

Shih-Chi Lin