Taiwan Semiconductor Manufacturing Comp. Ltd.

Shih-Chi Fu

Kuei-Shun Chen

Chia-Shiung Tsai

Ching-Sen Kuo

Gwo-Yuh Shiau

Wen-Chen Lu

Chi-Kang Chang

Jhon Jhy Liaw

Yen-Huei Chen

Yuan-Chih Hsieh

Feng-Jia Shiu

Min-Chang Liang

Fang Chen

Ren-Fen Tsui

Jieh-Jang Chen

Chung-Ming Wang

Chih-Hsiung Peng

Chi-Hung Liao

Tzong-Sheng Chang

Fei-Gwo Tsai

Jui-Ping Chuang

Meng-Wei Chen

Kai Tzeng

Hsueh-Yi Chung

Wei-Ti Hsu

Ting-Wei Chiang

Chih-Tsung Shih

Jung-Chan Yang

Bo-Tsun Liu

Chi-Hsin Lo

Yuan-Hung Liu

Cheng-I Huang

Chun-Chang Chen

Yung-Cheng Chen

Wang-Pen Mo

Tsung-Chih Chien

Tsung Chuan Lee

Sheng-Fang Cheng

Chi-Hua Fu

Chia-Tung Ho

Feng-Jia Shih

Kuotang Cheng

Shih-Chang Liu

Chung-Yi Yu

Chien-Chih Chou

Hung-Chang Hsieh

Ming-Chyi Liu

Hua Feng Chen

Min-Yann Hsieh

Chih-Ta Wu

Yuan-Hsiang Lung

Po-Hsueh Li

Yan-Tso Tsai

Chi-Wen Hsieh

Liang-Lung Yao

Tsung-Lin Yang

Chia-Shiung Tsia

Chien-Ping Hung

Ming-Ying Hsieh

Wen-Ting Chu

Yeur-Luen Tu

Chia-Ta Hsieh

Tzu-Hsuan Hsu

Kuo-Yin Lin

Shun-Shing Yang

Hung Chang Hsieh

Ying-Hao Su

Alex Hsu

Yu-Lun Liu

Chih-Yuan Chen

Yung-cheng Chen

Chen-Yan Li

Chien Hsien Tseng

Chloe Hsu

A method of fabricating a semiconductor device includes generating at least one photomask based on a layout and forming a plurality of active patterns on a substrate, using the at least one photomask. The layout includes a plurality of first patterns that extend parallel to each other in a first direction on a low-density region of the layout and a plurality of second patterns that extend parallel to each other in the first direction on a high-density region of the layout. The forming of the plurality of active patterns includes using the first patterns and the second patterns of the layout to respectively form a plurality of first active patterns and a plurality of second active patterns on the substrate.

Method and structure for mandrel and spacer patterning

An extreme ultraviolet (EUV) mask includes a multilayer Mo/Si stack comprising alternating Mo and Si layers disposed over a first major surface of a mask substrate, a capping layer made of ruthenium (Ru) disposed over the multilayer Mo/Si stack, and an absorber layer on the capping layer. The EUV mask includes a circuit pattern area and a particle attractive area, and the capping layer is exposed at bottoms of patterns in the particle attractive area.

Extreme ultraviolet mask and method of manufacturing the same

In a method of manufacturing a semiconductor device, a layout is prepared. The layout includes active region patterns, each of the active region patterns corresponding to one or two fin structures, first fin cut patterns and second fin cut patterns. At least one pattern selected from the group consisting of the first fin cut patterns and the second fin cut patterns has a non-rectangular shape. The layout is modified by adding one or more dummy active region patterns and by changing the at least one pattern to be a rectangular pattern. Base fin structures are formed according to a modified layout including the active region patterns and the dummy active region patterns. Part of the base fin structures is removed according to one of a modified layout of the first fin cut patterns and a modified layout of the second fin cut patterns.

Method of manufacturing a semiconductor device and semiconductor device

A semiconductor device includes a first fin, a first continuous fin and continuous gates. The first fin is formed on a substrate, and includes first and second portions that are spaced apart by a first recess. A side of the first portion and a side of the second portion are located at two sides of the first recess, respectively. The first continuous fin is formed on the substrate, and extends along the first portion, the first recess and the second portion. The continuous gates are formed on the substrate, and arranged to intersect the first continuous fin and the first fin in a layout view. A first number of the continuous gates are disposed across the first recess and each of the first number of the continuous gates is disposed between the two sides of the first recess in a layout view. A method is also disclosed herein.

Semiconductor device and layout thereof

A device includes a Static Random Access Memory (SRAM) array, and an SRAM cell edge region abutting the SRAM array. The SRAM array and the SRAM cell edge region in combination include first gate electrodes having a uniform pitch. A word line driver abuts the SRAM cell edge region. The word line driver includes second gate electrodes, and the first gate electrodes have lengthwise directions aligned to lengthwise directions of respective ones of the second gate electrodes.

SRAM circuits with aligned gate electrodes

A method includes receiving a device design layout and a scribe line design layout surrounding the device design layout. The device design layout and the scribe line design layout are rotated in different directions. An optical proximity correction (OPC) process is performed on the rotated device design layout and the rotated scribe line design layout. A reticle includes the device design layout and the scribe line design layout is formed after performing the OPC process.

Method of fabricating reticle

A method includes forming a first mandrel pattern and a second mandrel pattern. The first mandrel pattern includes at least first and second mandrels for a mandrel-spacer double patterning process. The second mandrel pattern includes at least a third mandrel inserted between the first and second mandrels. The first mandrel pattern and the second mandrel pattern include a same material. The first and second mandrels are merged together with the third mandrel to form a single pattern.

A semiconductor device includes a first active fin on a substrate; a second active fin on the substrate and separate from the first active fin; and a first fin stub on the substrate, wherein the first fin stub connects a first end of the first active fin and a first end of the second active fin, wherein the fin stub is lower than both the first and the second active fins in height, wherein from a top view the first active fin is oriented lengthwise in a first direction, and the first fin stub is oriented lengthwise in a second direction that is different from the first direction.

A method for exposing a wafer substrate includes forming a reticle having a device pattern. A relative orientation between the device pattern and a mask field of an exposure tool is determined based on mask field utilization. The reticle is loaded on the exposure tool. The wafer substrate is rotated based on an orientation of the device pattern. Radiation is projected through the reticle onto the rotated wafer substrate by the exposure tool, thereby imaging the device pattern onto the rotated wafer substrate.

A method includes the operations below. A first and second layout patterns corresponding to a first and second area are placed. Third layout patterns corresponding to a first continuous fin over the first area and second area, and corresponding to a second fin including separate portions spaced apart by a first recess over the first area are placed. A fourth layout pattern, corresponding to a dummy gate, at the recess portion and between the first layout pattern and the second layout pattern, is placed to generate a layout design of a semiconductor device. A side of the second area facing the first recess is substantially flat, and the semiconductor device is fabricated by a tool based on the layout design. A first length of the first continuous fin is equal to a sum of a second length of the second fin and a third length of the first recess.

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Zhudong, Taiwan

Shih-Chi Fu