Taiwan Semiconductor Manufacturing Comp. Ltd.

Shih-Chang Liu

Chia-Shiung Tsai

Chern-Yow Hsu

Chang-Ming Wu

Fu-Ting Sung

Yuan-Tai Tseng

Harry-Hak-Lay Chuang

Ming Chyi Liu

Wei Cheng Wu

Yu-Hsing Chang

Chung-Yen Chou

Wei-Hang Huang

Chung-Chiang Min

Ching-Pei Hsieh

Xiaomeng Chen

Ru-Liang Lee

Chi-Hsin Lo

Sheng-Chieh Chen

Chen-Jong Wang

Tsung-Hsueh Yang

Yeur-Luen Tu

Wen-Ting Chu

Lee-Chuan Tseng

Ming-Chyi Liu

Sheng-De Liu

Wei-Cheng Wu

Shih Pei Chou

Hung-Wen Hsu

Ming-Huei Shen

Yao-Wen Chang

Yung-Chang Chang

Yuan-Chih Hsieh

Jiech-Fun Lu

Shih-Wei Lin

Harry Hak-Lay Chuang

Ching-Chung Su

Chin-Yi Huang

Yi Jen Tsai

Zhiqiang Wu

Chung-Yi Yu

Fu-Chih Yang

Shu-Ting Tsai

Ya-Chen Kao

Kuei-Hung Shen

Chun-Han Tsao

Chern-yow Hsu

Ming-Hui Shen

Tsun Kai Tsao

Chien-Hong Chen

Sheng-Huang Huang

Yi-Shin Chu

Tsun-Kai Tsao

Chun-Tsung Kuo

Chia-Chieh Lin

Min-Yung Ko

Chia-Ta Hsieh

Yu-Wen Liao

Hung-Cheng Sung

Chen-Ming Huang

Shih-Chi Fu

Gwo-Yuh Shiau

Ching-Sheng Chu

Chang-Jen Hsieh

Po-ken Lin

Chu-Wei Chang

Yi-Jen Tsai

Chun-Wen Cheng

Tzu-Hsuan Hsu

Jiun-Lei Jerry Yu

Hsia-Wei Chen

Chi-Ming Chen

Yi-Chuan Teng

Yuan-Sheng Huang

Yuan-Hung Liu

Wen-I Hsu

Cheng-Yu Hsieh

Pei-Lun Wang

Chih-Jen Chan

Chi-Wei Ho

Fang-Lan Chu

Chun-wen Cheng

Wei-Tung Huang

Yi-chuan Teng

Cheng-Jong Wang

Sheng-Haung Haung

Lin Chia-Chieh

Hsieh Ching Pei

Chien-Ming Ku

Cheng-yu Hsieh

The present disclosure relates to a semiconductor device. The semiconductor device includes a first dielectric layer having a first region and a second region. A bottom electrode is at least partially arranged within the first region of the first dielectric layer. A memory element is over the bottom electrode and a top electrode is over the memory element. A second dielectric layer is over at least the first region of the first dielectric layer. The second dielectric layer surrounds the memory element and at least a part of the top electrode. A third dielectric layer is over the second region of the first dielectric layer and laterally adjacent to the second dielectric layer. A conductive interconnect is in the third dielectric layer and the second region of the first dielectric layer. The first dielectric layer has a different non-zero thickness within the first region than within the second region.

Method of forming memory cell

In some embodiments, the present disclosure relates to an integrated chip (IC), including a bottom electrode overlying an interconnect structure disposed within a lower inter-level dielectric (ILD) layer, a top electrode over the bottom electrode, a data storage structure between the top electrode from the bottom electrode, a conductive barrier layer directly overlying the interconnect structure, and a bottom electrode via (BEVA) vertically separating and contacting a bottom surface of the bottom electrode and a top surface of the conductive barrier layer. A maximum width of the BEVA is less than a width of the data storage structure.

Bottom electrode via and conductive barrier design to eliminate electrical short in memory devices

A semiconductor device includes: a first conductive plate and a second conductive plate disposed adjacent to the first conductive plate; a first insulating plate disposed over the first conductive plate and the second conductive plate; a third conductive plate disposed over the first insulating plate; a second insulating plate disposed over the third conductive plate; a fourth conductive plate disposed on one side of the second conductive plate opposite to the first conductive plate; a first conductive spacer disposed on the first insulating plate adjacent to the fourth conductive plate; a first conductive via penetrating the second insulating plate, the first insulating plate, and the first conductive plate, wherein the first conductive via is electrically coupled to the first conductive plate; and a second conductive via penetrating the fourth conductive plate, wherein the second conductive via is electrically coupled to the fourth conductive plate.

Semiconductor device and method of forming the same

Some embodiments pertain to a semiconductor device. The semiconductor device includes a semiconductor substrate including a trench extending downward into an upper surface of the semiconductor substrate. The trench includes a bottom surface and a plurality of scallops along sidewalls of the trench. An oxide layer lines the bottom surface and the sidewalls of the trench. The oxide layer has varying thicknesses along the sidewalls of the trench at different depths. The varying thicknesses step down at discrete increments as a depth into the trench increases.

High aspect ratio bosch deep etch

The present disclosure provides a semiconductor structure and a method for fabricating semiconductor structure. The semiconductor structure includes a first device, configured to be a complementary metal oxide semiconductor device, wherein the first device includes a substrate, a multi-layer structure disposed on the substrate, a first hole, defined between a first end with a first circumference and a second end with a second circumference, a second hole, aligned to the first hole and defined between the second end and a third end with a third circumference, wherein the third circumference is larger than the first circumference and the second circumference, and a second device, configured to be a micro-electro mechanical system device and bonded to the first device, wherein a first chamber is between the first device and the second device, and the first end links with the first chamber, and a sealing object configured to seal the second hole.

Semiconductor device and method for fabricating the same

In some embodiments, the present disclosure relates to an integrated chip (IC), including a bottom electrode overlying an interconnect structure disposed within a lower inter-level dielectric (ILD) layer, a top electrode over the bottom electrode, a data storage structure between the top electrode from the bottom electrode, a conductive barrier layer overlying the interconnect structure, and a bottom electrode via (BEVA) vertically separating and contacting a bottom surface of the bottom electrode and a top surface of the conductive barrier layer. A maximum width of the BEVA is less than a width of the data storage structure.

The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a source/drain region arranged within a substrate. A select gate and a memory gate are arranged over the substrate. An inter-gate dielectric structure is arranged between the memory gate and the select gate. A conductive contact is disposed on the source/drain region and vertically extends from a bottom of the select gate to a top of the select gate. The select gate is closer to the conductive contact than the memory gate. The select gate has a first outermost sidewall that faces away from the memory gate and a second outermost sidewall that faces the memory gate. The first outermost sidewall is taller than the second outermost sidewall.

Split gate memory device and method of fabricating the same

A device comprises a control gate structure and a memory gate structure over a substrate, a charge storage layer formed between the control gate structure and the memory gate structure, a first spacer along a sidewall of the memory gate structure, a second spacer along a sidewall of the control gate structure, an oxide layer over a top surface of the memory gate structure, a top spacer over the oxide layer, a first drain/source region formed in the substrate and adjacent to the memory gate structure and a second drain/source region formed in the substrate and adjacent to the control gate structure.

Memory devices and method of fabricating same

A memory cell with a hard mask and a sidewall spacer of different material is provided. The memory cell may be manufactured by a method comprising forming a multi-layer stack and patterning the same to form the hard mask layer, the top electrode layer and the switching dielectric layer to form a hard mask, a top electrode and a switching dielectric. A sidewall spacer is formed alongside the hard mask, the top electrode, and the switching dielectric with a material different than the hard mask. The bottom electrode layer is patterned according to the sidewall spacer to form a bottom electrode. A dielectric layer is formed surrounding the bottom electrode, the sidewall spacer and overlying the hard mask. An etch is performed followed by a conductive material filling to form a top electrode via extending through the dielectric layer and the hard mask to reach on the top electrode.

Memory device having via landing protection

A method for fabricating a semiconductor memory device is provided. The method includes: etching a first region of the semiconductor memory device to expose a first capping layer; forming a second capping layer on the first capping layer; etching a portion of the first capping layer and a portion of the second capping layer to form a first trench reaching a first metal line; and forming a second metal line in the first trench to contact the first metal line.

Semiconductor memory device and method for fabricating the same

Depositing a side slab structure on a cladding layer before etching a supporting dielectric prevents tapering of a silicon waveguide during etching of the supporting dielectric and a substrate. For example, the side slab structure may be deposited over the silicon waveguide and the cladding layer after etching the cladding layer. As a result, when an electronic device is integrated ex situ on the substrate, wave intensity and/or total internal reflection is improved, which improves an efficiency of the electronic device.

Semiconductor waveguides and methods of forming the same

Some embodiments relate to an integrated circuit including a semiconductor substrate and an interconnect structure disposed over the semiconductor substrate. The interconnect structure includes a plurality of dielectric layers and a plurality of metal layers that are stacked over one another in alternating fashion. The plurality of metal layers include a lower metal layer and an upper metal layer disposed over the lower metal layer. A bottom electrode is disposed over and in electrical contact with the lower metal layer. A dielectric layer is disposed over an upper surface of the bottom electrode. A top electrode is disposed over an upper surface of the dielectric layer and is in direct electrical contact with a lower surface of the upper metal layer.

Techniques for MRAM MTJ top electrode connection

A memory device includes a first metal structure, a magnetic tunnel junction (MTJ) structure, a second metal structure, a first spacer, and a second spacer. The MTJ structure is over the first metal structure. The second metal structure is over the MTJ structure. The first spacer is over a first sidewall of the second metal structure. The second spacer is over a second sidewall of the second metal structure. The second spacer has a top surface higher than a top surface of the first spacer.

Memory device with composite spacer

A semiconductor structure includes an Nmetal layer, a diffusion barrier layer over the Nmetal layer, a first deposition of bottom electrode material over the diffusion barrier layer, a second deposition of bottom electrode material over the first deposition of bottom electrode material, a magnetic tunneling junction (MTJ) layer over the second deposition of bottom electrode material, a top electrode over the MTJ layer; and an (N+1)metal layer over the top electrode; wherein the diffusion barrier layer and the first deposition of bottom electrode material are laterally in contact with a dielectric layer, the first deposition of bottom electrode material spacing the diffusion barrier layer and the second deposition of bottom electrode material apart, and N is an integer greater than or equal to 1. An associated electrode structure and method are also disclosed.

Semiconductor structure, electrode structure and method of forming the same

The present disclosure provides a semiconductor structure, including an Nmetal layer over a transistor region, where N is a natural number, and a bottom electrode over the Nmetal layer. The bottom electrode comprises a bottom portion having a first width, disposed in a bottom electrode via (BEVA), the first width being measured at a top surface of the BEVA, and an upper portion having a second width, disposed over the bottom portion. The semiconductor structure also includes a magnetic tunneling junction (MTJ) layer having a third width, disposed over the upper portion, a top electrode over the MTJ layer and an (N+1)metal layer over the top electrode. The first width is greater than the third width.

Semiconductor structure and method of forming the same

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Alian, Taiwan

Shih-Chang Liu