Ememory Technology Inc.

Novatek Microelectronics Corp.

Shih-Chan Huang

Ching-Hsiang Hsu

Chun-Hung Lin

Yen-Cheng Cheng

Yen-Hsin Lai

Ming-Shan Lo

Yi-Hung Li

Hsin-Ming Chen

Shih-Jye Shen

Wei-Zhe Wong

Chih-Wei Chen

Ming-Chou Ho

Chun-Hung Lu

Ko Ho Lin

The disclosure provides a touch device and an operation method thereof. A touch panel of the touch device is divided into a plurality of stylus connection areas. During a first discovery period, the stylus connection areas detect a stylus one by one in a first scan order. When the stylus is located in one of the stylus connection areas (a hit area), the first discovery period is ended to enter a normal period, and the hit area establishes a connection to the stylus. When the connection between the stylus and the touch panel is interrupted, the normal period is ended to enter a second discovery period, and the first scan order is adjusted to a second scan order according to the hit area in the normal period. During the second discovery period, the stylus connection areas detect the stylus one by one in the second scan order.

Touch device and method with scan order of connection areas according to hit area where stylus is located

A detection method for a touch device includes transmitting a first uplink signal conforming to a first protocol of a first active stylus and transmitting a second uplink signal conforming to a second protocol of a second active stylus. A chronological sequence of the first uplink signal and the second uplink signal is based at least in part on whether the first active stylus or the second active stylus has just left a detection range of the touch device.

Detection method and driving circuit thereof

A random code generator includes a differential cell array, a power circuit, a voltage detector, a control circuit and a read/write circuit. The power circuit provides a supply voltage to a node. The differential cell array includes plural differential cells. Each differential cell includes two sub-cells. The two sub-cells have process variations. During the enrollment, one sub-cell is programmed, and the other sub-cell is subjected to a program inhibition. In addition, a random code is generated according to the storage state of the differential cell.

Random code generator with differential cells and associated control method

A single-poly nonvolatile memory (NVM) cell includes a PMOS select transistor on a semiconductor substrate and a PMOS floating gate transistor series connected to the PMOS select transistor. The PMOS floating gate transistor comprises a floating gate and a gate oxide layer between the floating gate and the semiconductor substrate. A protector oxide layer covers and is indirect contact with the floating gate. A contact etch stop layer is disposed on the protector oxide layer such that the floating gate is isolated from the contact etch stop layer by the protector oxide layer.

Single-poly nonvolatile memory cell

According to one embodiment, a single-poly nonvolatile memory (NVM) cell includes a PMOS select transistor on a semiconductor substrate and a PMOS floating gate transistor series connected to the PMOS select transistor. The PMOS floating gate transistor comprises a floating gate and a gate oxide layer between the floating gate and the semiconductor substrate. A protector oxide layer covers and is in direct contact with the floating gate. A contact etch stop layer is disposed on the protector oxide layer such that the floating gate is isolated from the contact etch stop layer by the protector oxide layer.

Nonvolatile memory structure and fabrication method thereof

A CMOS-compatible read only memory (ROM) includes a first single-poly PMOS transistor that is serially electrically connected to a second single-poly PMOS transistor for recording digital data &ldquo;1&rdquo; or digital data &ldquo;0&rdquo;. The first and second single-poly PMOS transistors are both formed on an N-well of a P-type substrate. The first single-poly PMOS transistor includes a select gate electrically connected to a word line, a first P&plus; source doping region electrically connected to a source line, and a first P&plus; drain doping region. The second single-poly PMOS transistor includes a floating gate, a second P&plus; source doping region electrically connected to the first P&plus; drain doping region, and a second P&plus; drain doping region electrically connected to a bit line. The second P&plus; source doping region and the second P&plus; drain doping region define a floating gate channel region under the floating gate. A fast FPLD-to-ROM conversion method is also disclosed. After the final software code is fixed and the addresses where the memory units to be coded are determined, the FPLD are transformed into a ROM by either changing the layout of a photo mask that is used to define polysilicon gates to cancel the pre-selected floating gates according to the fixed software code, or by ion implanting the pre-selected floating gate channel regions underneath those floating gates where the memory units are to be coded.

Growing community of inventors

Hsinchu County, Taiwan

Shih-Chan Huang