Renesas Electronics Corporation

Hitachi, Ltd.

Renesas Technology Corp.

Other

Hitachi Ulsi Systems Co., Ltd.

Hitachi Microcomputer System, Ltd.

Shigezumi Matsui

Koichiro Ishibashi

Kenichi Osada

Masanao Yamaoka

Motoo Suwa

Ikuya Kawasaki

Takafumi Betsui

Norihiko Sugita

Naoto Taoka

Yoshiharu Fukushima

Susumu Narita

Masato Nemoto

Hisashi Shiota

Shinichi Yoshioka

Atsushi Kiuchi

Peter M Lee

Ryoichi Sano

Takashi Satou

Gouichi Yokomizo

Satoshi Nakamura

Satoshi Masuda

Yasuyuki Murakami

Takashi Sato

Kazuyuki Sakata

Yuichi Takitsune

Kunihiko Nishiyama

Ryo Sudo

Yasunori Matsumoto

Tsuyoshi Yaguchi

Kenzo Kuwabara

Hiroshi Takeda

Yoshinori Miyaki

Kiyoshi Hasegawa

Akinobu Watanabe

Yoshiyuki Kondo

Takanobu Naruse

Toru Hayashi

Susumu Kaneko

Kouji Hashimoto

Haruyasu Okubo

Mitsuyoshi Yamamoto

Mitsuya Kinoshita

A microcomputer provided on a rectangular semiconductor board has memory interface circuits. The memory interface circuits are separately disposed in such positions as to extend along the peripheries of the semiconductor board on both sides from one corner as a reference position. In this case, limitations to size reduction imposed on the semiconductor board can be reduced compared with a semiconductor board having memory interface circuits only on one side. Respective partial circuits on each of the separated memory interface circuits have equal data units associated with data and data strobe signals. Thus, the microcomputer has simplified line design on a mother board and on a module board.

Data processing device

A logic circuit in a system LSI (Large Scale Integrated Circuit) is provided with a power switch so as to cut off the switch at the time of standby, reducing leakage current. At the same time, an SRAM (Static Random Access Memory) circuit of the system LSI controls a substrate bias to reduce leakage current.

Lower-power semiconductor memory device

A logic circuit in a system LSI is provided with a power switch so as to cut off the switch at the time of standby, reducing leakage current. At the same time, an SRAM circuit of the system LSI controls a substrate bias to reduce leakage current.

Semiconductor device

A semiconductor device having static memory cells is designed to reduce leakage current and power consumption. The static memory cells are coupled to word lines and bit lines, and the word lines are coupled to word drivers. A first P channel MOS transistor (MOS power switch) has a gate coupled to receive a first control signal, and a second P channel MOS transistor (MOS power switch) has a gate coupled to receive a second control signal different from the first control signal. Source-drain paths of the first and second P channel MOS transistors (MOS power switches) are coupled to respective voltage supply points for different parts of the semiconductor device, such as voltage supply points for the memory cells and the word drivers, or voltage supply points for a logic circuit and the word drivers.

Low power semiconductor memory device

Low-power semiconductor device

A semiconductor device is provided. The semiconductor device includes a logic circuit, an SRAM circuit coupled to a power line, and a switch coupled between the logic circuit and the power line. Before the switch is changed to an off position, a part of information held in the logic circuit is transferred to the SRAM circuit.

Semiconductor device with logic circuit, SRAM circuit and standby state

Signals outputted from an I/O buffer with a parallel drive configuration are stabilized for reliability enhancement. Each I/O cell has a complementary I/O cell that outputs one output signal as a complementary signal made up of a non-inverted signal and an inverted signal. Two I/O cells are coupled in parallel. Output portions of first inverters are coupled together through a first wiring; and output portions of second inverters are coupled together through a second wiring. The first wiring is formed on the lower side of the I/O cells so that it is astride the two I/O cells, and the second wiring is formed above the first wiring so that it is astride the two I/O cells. The wirings are laid out so that the wiring length of the first wiring and the wiring length of the second wiring are substantially equal to each other.

Semiconductor device including chip with complementary I/O cells

Microcomputer having memory interface circuits and memory devices on a module board

Growing community of inventors

Nishitokyo, Japan

Shigezumi Matsui