Rohm Co., Ltd.

Shigeyuki Ueda

Kazutaka Shibata

Tadahiro Morifuji

Junichi Hikita

Osamu Miyata

Tomoharu Horio

Minoru Hirai

Goro Nakatani

Katsumi Sameshima

Nobuhisa Kumamoto

Toshio Enami

Disclosed is a semiconductor device suppressed in decrease of reliability. The semiconductor device comprises an electrode pad portion () formed on the upper surface of a semiconductor substrate (), a passivation layer () so formed on the upper surface of the semiconductor substrate () as to overlap a part of the electrode pad portion () and having a first opening portion () where the upper surface of the electrode pad portion () is exposed, a barrier metal layer () formed on the electrode pad portion (), and a solder bump () formed on the barrier metal layer (). The barrier metal layer () is formed such that an outer peripheral end () lies within the first opening portion () of the passivation layer () when viewed in plan.

Semiconductor device

A semiconductor chip includes an electrode pad on a substrate, a barrier metal layer on the electrode pad, a bump electrode, a first protection layer formed on the substrate, and a second protection layer having an opening. The first protection layer overlaps part of the electrode pad. The second protection layer covers a region over the first protection layer and a region over the electrode pad. The upper surface of the second protection layer has an arc surface. The thickness between the arc surface and the electrode pad as seen in a sectional view is gradually large from the rim of the opening to the rim of the electrode pad. The rate of change of the thickness is higher at the rim of the opening than at the rim of the electrode pad.

Disclosed is a semiconductor device suppressed in decrease of reliability. The semiconductor device comprises an electrode pad portion formed on the upper surface of a semiconductor substrate, a passivation layer so formed on the upper surface of the semiconductor substrate as to overlap a part of the electrode pad portion and having a first opening portion where the upper surface of the electrode pad portion is exposed, a barrier metal layer formed on the electrode pad portion, and a solder bump formed on the barrier metal layer. The barrier metal layer is formed such that an outer peripheral end lies within the first opening portion of the passivation layer when viewed in plan.

A semiconductor chip in which a through hole penetrating through its surface and reverse surface is formed in a scribe line region in the vicinity of an active region where a functional device is formed, and a conductive member is arranged in the through portion. The through portion may be a groove opening sideward on a sidewall surface of the semiconductor chip. The through portion may be a through hole blocked from a side part of the semiconductor chip. The semiconductor chip may further include wiring for electrically connecting an internal circuit formed in the active region and the conductive member to each other.

Semiconductor chip and semiconductor device using the same, and method of fabricating semiconductor chip

A semiconductor chip having a functional bump provided on a surface of a semiconductor substrate thereof for electrical connection between an internal circuit thereof and a solid device, and a dummy bump not serving for the electrical connection between the internal circuit and the solid device. The dummy bump may be a stress relieving bump for relieving stresses exerted thereon. The dummy bump may be connected to a low impedance portion. The functional bump and the dummy bump may be provided on a surface protective film. In this case, the dummy bump is provided on a recess formed in the surface protective film.

Semiconductor chip and production thereof, and semiconductor device having semiconductor chip bonded to solid device

A semiconductor chip which is to be overlapped with and joined to a surface of another solid device. The semiconductor chip has a surface protective film for covering internal wiring, an external connection pad which is formed by partially exposing the internal wiring from the surface protective film, and a wire connecting portion which is formed using a metal material having oxidation resistance on the external connection pad and to which a wire for electrical connection to an external terminal is connected. It is preferable that the semiconductor chip further has an internal connection pad used for connection to the solid device and a bump formed on the pad.

Semiconductor chip and method of producing the same

A production process for a semiconductor device having a metal electrode on a semiconductor substrate thereof. A metal electrode portion is formed on a surface of another substrate for electrode transfer. Then, the metal electrode portion is transferred from the electrode transfer substrate onto the semiconductor substrate by pressing together the electrode transfer substrate and the semiconductor substrate. The electrode transfer substrate has, for example, a seed film provided on the surface thereof, and the formation of the metal electrode portion on the electrode transfer substrate may be achieved by depositing a material for the metal electrode on the seed film by plating. The electrode transfer substrate may have an insulating film which covers a surface of the seed film except a portion thereof on which the metal electrode portion is to be formed.

Growing community of inventors

Kyoto, Japan

Shigeyuki Ueda