Sanyo Electric Co., Ltd.

Panasonic Intellectual Property Management Co., Ltd.

Shigeyuki Okamoto

Daijiro Inoue

Yasuhiko Nomura

Yukihiro Yoshimine

Yasufumi Tsunomura

Kunio Takeuchi

Masayuki Hata

Ryoji Hiroyama

Tadao Toda

Yasuyuki Bessho

Tsutomu Yamaguchi

Hiroshi Kanno

Shigeharu Taira

Haruhisa Hashimoto

Hisanori Uda

Kiyoshi Oota

Atsushi Saita

Koutarou Furusawa

Shingo Kameyama

Koji Tominaga

Noriaki Matsuoka

Ryouji Hiroyama

A solar cell module includes a plurality of solar cellsconnected to each other in a way that bus bar electrodeformed on surfaces of adjacent solar cellsare connected to each other with wiring members. The bus bar electrodeis embedded in the wiring member, and the solar celland the wiring memberare bonded together with a resin.

Solar cell module and solar cell module manufacturing method

In a solar cell module, a plurality of solar cells are provided between a front surface protection member and a back surface protection member and bus bar electrodesof the plurality of solar cells are electrically connected to each other by wiring members. The solar cell module includes an adhesive layer made of a resincontaining a plurality of conductive particles, the adhesive layer provided between each of the bus bar electrodesand the wiring member. Each of the bus bar electrodesand the corresponding wiring memberare electrically connected by the plurality of conductive particles. The resincovers side surface of each of the bus bar electrodesand configured to bond the wiring memberwith the surface of a photoelectric conversion body

Solar cell module

A solar battery module is provided with a plurality of solar battery cells which are connected to each other by connecting bus bar electrodes () formed on the surfaces of the adjacent solar battery cells with wiring material (). The bus bar electrode () is embedded in the wiring material (), and the solar battery cell () and the wiring material () are bonded with a resin.

With the method for manufacturing the solar cell moduleaccording to the present embodiment, the width Wof the connection region C in which the wiring memberand the connecting electrodeare electrically connected is set to be larger than the substantially half of the width Wof the wiring memberin the thermocompression bonding process of the wiring memberusing the resin adhesiveincluding the particlesonto the principal surface of the solar cell

Solar cell module and method for manufacturing the same

A semiconductor device capable of stabilizing operations thereof is provided. This semiconductor device comprises a substrate provided with a region having concentrated dislocations at least on part of the back surface thereof, a semiconductor element layer formed on the front surface of the substrate, an insulator film formed on the region of the back surface of the substrate having concentrated dislocations and a back electrode formed to be in contact with a region of the back surface of the substrate other than the region having concentrated dislocations.

Method of fabricating a semiconductor device with a back electrode

Semiconductor device and method of fabricating the same

Semiconductor device

A semiconductor laser device capable of improving heat dissipativity, simplifying the fabrication process and improving the fabrication yield is obtained. This semiconductor laser device comprises a semiconductor layer formed on an emission layer while constituting a convex ridge portion, a current blocking layer consisting of a semiconductor formed to cover at least the side surfaces of the ridge portion, a first metal electrode formed to be in contact with the upper surface of the ridge portion and convex support portions arranged on both sides of the ridge portion at a prescribed interval from the ridge portion.

Semiconductor laser device and method of fabricating the same

A semiconductor laser device is characterized in that an angle &#x3b8; of inclination formed by the side surfaces of a ridge portion and a lower part of the ridge portion is at least 70&#xb0; and not more than 117&#xb0;, a p-type cladding layer is made of AlGaAs, a first current blocking layer is made of AlGaAs, the distance between an emission layer and the first current blocking layer satisfies the relation of t&#x2266;0.275/(1&#x2212;(X2&#x2212;X1)) assuming that t represents the distance, and a lower width W of the ridge portion is at least 2 &#x3bc;m and not more than 5 &#x3bc;m.

Semiconductor laser device and method of manufacturing the same

A semiconductor laser device capable of improving reliability is obtained in a structure formed by mounting a semiconductor laser element on a submount (base) in a junction-down system. This semiconductor laser device comprises a first electrode layer formed on the surface of a semiconductor element including an emission layer to have a shape comprising recess portions and projection portions, a base mounted with the semiconductor element, and a plurality of low melting point metal layers provided between the first electrode layer formed on the surface of the semiconductor element and the base for bonding the first electrode layer formed on the surface of the semiconductor element and the base to each other. Thus, the plurality of low melting point metal layers easily embed clearances resulting from the shape comprising recess portions and projection portions of the surface of the semiconductor element dissimilarly to a case of employing a single low melting point metal layer.

An n-GaAs current blocking layer is formed on a p-AlGaInP first cladding layer, on sides of a ridge portion and in a region on the upper surface of the ridge portion above a window region. Raised portions are formed in a p-GaAs cap layer in regions in the vicinity of facets, while raised regions are formed in the regions of a first electrode in the vicinity of the facets. A second electrode having a thickness larger than the height of the raised regions is formed on the region between the raised regions of the first electrode.

Semiconductor laser device and manufacturing method thereof

A plurality of FETs have their respective gates connected to each other through a first line and their respective drains connected to each other through a second line. A gate bias is applied to the gate of each FET through the first line and a drain bias is applied to the drain of each FET through the second line. A first matching circuit includes first capacitors connected to the signal path, inductors each connected between one end of each first capacitor and the ground potential, and second capacitors each connected between the other end of each first capacitor and the ground potential. The second matching circuit includes first capacitors each connected to the signal path, second capacitors each connected between one end of each first capacitor and the ground potential, and inductors each connected between the other end of each first capacitor and the ground potential.

Growing community of inventors

Kobe, Japan

Shigeyuki Okamoto