Kabushiki Kaisha Toshiba

Tokyo Shibaura Denki Kabushiki Kaisha

Kabushiki Kasiha Toshiba

Shigeyoshi Watanabe

Fujio Masuoka

Takehiro Hasegawa

Koji Sakui

Yukihito Oowaki

Fumio Horiguchi

Tsuneaki Fuse

Daisaburo Takashima

Riichiro Shirota

Masaki Momodomi

Seiichi Aritome

Shinichiro Shiratake

Akihiro Nitayama

Tomoharu Tanaka

Tetsuo Endoh

Yasuo Itoh

Ryu Ogiwara

Ryouhei Kirisawa

Sumio Tanaka

Toshiki Seshita

Kazunori Ohuchi

Ryozo Nakayama

Yoshihisa Iwata

Hiroshi Iwahashi

Takeshi Hamamoto

Katsuhiko Hieda

Ryo Fukuda

Tohru Ozaki

Tohru Furuyama

Syuso Fujii

Mitsuo Saito

Takahiko Hara

Mitsugi Ogura

Kenji Numata

Kazumasa Sunouchi

Satoshi Inoue

Tatsuo Ikawa

Masako Yoshida

Masashi Wada

Ken-ichi Maeda

Masako Ohta

Masahiko Chiba

Tetsuro Endoh

Mitsugi Oguara

Here is disclosed a dynamic semiconductor memory of high integration density, which has parallel word lines and parallel bit lines formed on a substrate. The bit lines include a pair of bit lines. A memory cell is coupled to a word line and to one bit line of the bit-line pair. The memory cell is composed of MOSFETs of a submicron size. A sense amplifier section is connected to the pair of bit lines, and senses and amplifies the potential difference between the pair of bit lines in a data readout mode. The amplifier section has a BIMOS structure, having MOSFETs and bipolar transistors. It has a driver section comprised of bipolar transistors.

Dynamic random access memory device

A semiconductor device includes a bipolar transistor whose emitter-collector voltage is set to satisfy a condition I,<I,according to a voltage applied across a base and emitter where I,is the base current flowing through a base-emitter path in a forward direction, and I,is the base current flowing through a collector-base path in a reverse direction.

Semiconductor device

Semiconductor device including a bipolar transistor biased to produce a negative base current by the impact ionization mechanism

A sense amplifier is connected between memory cell arrays, a re-writing register is arranged adjacent to the sense amplifier, first transfer gates are disposed between the sense amplifier and the memory cell arrays, second transfer gates are provided between bit lines of the memory cell arrays and global bit lines, and a gate control circuit for controlling the transfer gates is provided. When readout data is written into the register, the node of the sense amplifier is electrically separated from the bit lines and global bit lines.

NAND-type dynamic RAM having temporary storage register and sense

A semiconductor memory device includes active regions arranged on a semiconductor substrate such that those of the active regions which are adjacent in the word line direction deviate in the bit line direction, MOS transistors respectively formed in the active regions and each having a source and a drain one of which is connected to the bit line, a plurality of trenches each arranged to another set of source an drain regions and arranged to deviate in the word line direction in the respective active regions, those of the trenches which are adjacent with a through word line disposed therebetween being arranged to deviate in the bit line direction so as to be set closer to each other, a plurality of storage electrodes respectively formed in the trenches with capacitor insulative films disposed therebetween, and connection electrodes arranged between the word lines and each connecting the other of the source and drain to the storage electrode.

Dynamic random access memory device with the combined open/folded

A semiconductor memory device of the present invention comprises a plurality of word lines formed on a substrate, a plurality of bit lines perpendicular to the word lines and divided into bit-line groups in the column direction along the word line, each group containing three bit lines, and arrays of memory cells arranged at the intersections of word lines and bit lines, wherein two memory cells are placed at two of every three adjacent intersections arranged in each of the row and column directions, and where these memory cell arrays are divided into subarrays in the row direction, each of the cell arrays is divided into cell blocks in the row direction, two of the three bit lines in each bit-line group along the bit line are crossed each other between adjacent cell blocks, and a plurality of sense amplifiers are placed between adjacent cell arrays so as to correspond to cell blocks.

In a semiconductor memory device wherein a plurality of memory cell units formed by connecting a plurality of memory cells in series are provided and each of the memory cell units is connected to a bit line, the semiconductor memory device comprises control circuit for directly reading data of a register cell during a reading operation when the previous row address designates the same memory cell as the present row address, and a data changing controlling circuit for changing data of an arbitrary memory cell of the memory cell unit to data of the memory cell closest to the bit line contact in the memory cell unit, and a row decoder for corresponding row addresses which select the memory of memory cell units, to the upper addresses than the parts of the row addresses which select a memory unit among the memory cell units.

Semiconductor memory device

A sense amplifier is connected between memory cell arrays, a re-writing register is arranged in position adjacent to the sense amplifier, transfer gates are disposed between the sense amplifier and the memory cell arrays, transfer gates are provided between bit lines of the memory cell arrays and global bit lines, and a gate control circuit for controlling the transfer gates is provided. When readout data is written into the register, the node of the sense amplifier is electrically separated from the bit lines and global bit lines.

A dynamic random access memory device includes a semiconductor substrate, a plurality of parallel word lines on the substrate, and a plurality of pairs of bit lines transverse to the word lines on the substrate. An array of one-transistor memory cells are selectively arranged at the cross points as defined between the word lines and the bit lines. The array is subdivided into a plurality of subarray sections. A sense amplifier section is connected to the bit lines. The sense amplifier section includes first and second sense amplifier circuits. Adjacent bit-line pairs of the bit lines include a first bit-line pair and a second bit-line pair, one of which has a folded bit-line arrangement being included in a certain subarray section to be connected to the first sense amplifier circuit, and the other of which has an open bit-line arrangement that extends into the subarray section and another subarray section adjacent thereto, and is connected to the second sense amplifier circuit.

An erasable programmable read-only memory with NAND cell structure includes NAND cell blocks, each of which has a selection transistor connected to the corresponding bit line and a series array of memory cell transistors, and a switching transistor connected between the series array of memory cell transistors and ground. Each cell transistor has a floating gate and a control gate. Word lines are connected to the control gates of the cell transistors. In a data writing mode, a selection transistor of a certain cell block containing a selected cell is rendered conductive, so that this cell block is connected to the corresponding bit line. Under such a condition, a decoder circuit stores a desired data (a logic 'one' e.g.) in the selected cell, by applying an 'H' level voltage to the bit line, applying an 'L' level voltage to a word line connected to the selected cell, applying the 'H' level voltage to a memory cell or cells positioned between the selected cell and the bit line, and applying the 'L' level voltage to a memory cell or cells positioned between the selected cell and the ground. The selection transistor and switching transistor for a corresponding series array of memory cell transistors have different channel lengths to reduce punch through.

Non-volatile semiconductor memory with NAND cell structure and switching

A semiconductor memory device comprises an array of memory cell units, each of which has a plurality of MOS transistors connected in series and a plurality of information storage capacitors corresponding in number to the MOS transistors and each having its one end connected to the source of a corresponding one of the MOS transistors, and a plurality of register groups each of which is adapted to temporarily store information stored in one of the memory cell units for each column of the array in order to read from and write into each memory cell unit.

Semiconductor memory device having register groups for writing and

A semiconductor device connected between first and second wiring lines comprises a semiconductor substrate, a first semiconductor column formed by etching the substrate by a predetermined depth, a second semiconductor column formed by etching the substrate by a predetermined depth, with a predetermined distance set from the first semiconductor column, a first gate electrode formed around a side wall of the first semiconductor column with an insulating layer interposed, a second gate electrode formed around a side wall of the second semiconductor column with an insulating layer interposed, a first diffusion layer functioning as one of a source and a drain, the first diffusion layer being formed at a top portion of the first semiconductor column and connected to the first wiring line, a second diffusion layer functioning as another of the source and the drain, the second diffusion layer being formed at a top portion of the second semiconductor column and connected to the second wiring line, and a diffusion layer functioning as one of a source and a drain, the diffusion layer being formed at bottom portions and peripheral portions of the bottom portions of the first and second semiconductor columns and shared by the first and second semiconductor columns.

Semiconductor device with vertical transistors connected in series

A process for forming an array of FATMOS transistors serving as memory cells of a NAND cell type EEPROM. A multi-layered structure is provided on a substrate with two stacked conductive layers insulated by an intermediate insulative layer, the first or inner conductive layer being insulated by a first insulative layer from the substrate, the second or outer conductive layer being covered with a second insulative layer. The second insulative layer is etched to define a first array of etched layer portions. A photoresist layer is deposited and etched to define a second array of layer portions, each of which is positioned between two neighboring ones of the first array of layer portions. The multi-layered structure is etched with the first and second layer portions being as a mask, to thereby form an array of a plurality of pairs of insulated gate electrodes above the substrate. A chosen impurity is doped into the substrate with the insulated gate electrodes serving as a mask to thereby form impurity-doped regions in the substrate.

Process for forming arrayed field effect transistors highly integrated

A bipolar transistor Q.sub.1 having a collector formed of a substrate region SUB of a MOS transistor M.sub.1, a base formed of the drain region of the MOS transistor and an emitter formed on the base and connected to a bit line BL is connected between the bit line BL and a memory cell MC formed of the MOS transistor M.sub.1 and and a capacitor C.sub.1 and the current amplifying operation of a bipolar transistor is used for data readout.

Dynamic semiconductor memory device having high integration density

Growing community of inventors

Yokohama, Japan

Shigeyoshi Watanabe