Fujitsu Corporation

Fujitsu Semiconductor Limited

Fujitsu Microelectronics Limited

Shigetoshi Wakayama

Junji Ogawa

Kohtaroh Gotoh

Hirotaka Tamura

Miyoshi Saito

Hisakatsu Araki

Tsz-Shing Cheung

Hisakatsu Yamaguchi

Masato Suga

Hiroyuki Kato

Mitsuaki Igeta

Mutsuaki Kai

Yoshio Hirose

Hiroshi Okano

Seiji Endou

Toshiharu Nozawa

Matsuaki Kai

A design support program executed by a computer includes operations of: locating at least one via hole for coupling target wiring in a first layer in circuit information to wiring in a second layer being different form the first layer; calculating an area of the target wiring based on a length and a width of the target wiring; setting a division condition based on the area and a number of the via hole; dividing the target wiring into divided wirings at a position other than a position where the via hole is provided based on the division condition; generating connection information indicating a connection relationship between the divided wirings and limitation information for coupling the divided wirings via a wiring in a third layer being different from the first layer; and outputting the connection information, the limitation information and circuit information obtained after dividing.

Support program, design support system, and design support method

A semiconductor integrated circuit device has a command decoder for issuing a control command in accordance with a supplied control signal, a DRAM core, and a timing adjusting circuit for supplying the control command, set active for a predetermined period, as a DRAM control signal to the DRAM core. The timing adjusting circuit generates n different clocks that are respectively shifted in phase with respect to a supplied reference clock, and generates the DRAM control signal by setting the control command active in a prescribed operation cycle for only a period starting at a first predetermined clock pulse of a first clock of the n clocks and ending at a second predetermined clock pulse of a second clock of the n clocks. In this way, timing design with relatively high accuracy of adjustment can be done in a short period.

Phase interpolator for a timing signal generating circuit

A multilayer interconnection structure of a semiconductor device includes a first guard ring extending continuously along a periphery of a substrate and a second guard ring extending continuously in the multilayer interconnection structure along the periphery so as to be encircled by the first guard ring and so as to encircle an interconnection pattern inside the multilayer interconnection structure, wherein the first and second guard rings are connected with each other mechanically and continuously by a bridging conductor pattern extending continuously in a band form along a region including the first and second guard rings when viewed in the direction perpendicular to the substrate.

Semiconductor device having a guard ring

Timing signal generating circuit with a master circuit and slave circuits

A capacitor has a MOS gate structure in which a gate insulating film is held between a gate terminal and a ground terminal as a dielectric. A switch unit is connected between the gate terminal and a power supply. The ground terminal is connected to a ground. A switch control circuit that switches a state of the switch unit between a conductive state and a nonconductive state is provided. A predetermined voltage and a voltage of the gate terminal are input to a non-inverting input terminal and an inverting input terminal of the switch control circuit, respectively. The switch unit is conductive when the voltage of the gate terminal is higher than the predetermined voltage, and nonconductive when the voltage of the gate terminal is lower than the predetermined voltage.

Semiconductor device including capacitor having decoupling capacity

An input circuit writes an expected value to one end of an evaluation wiring. A latch circuit latches a logic level of the other end of the evaluation wiring. A first switch circuit connects an output of the input circuit to the input of the latch circuit. A second switch circuit connects the output of the input circuit to the one end of the evaluation wiring. A third switch circuit connects the other end of the evaluation wiring to the input of the latch circuit. By turning on, off, and off the first to third switch circuits, respectively, the output of the input circuit is directly connected to only the input of the latch circuit. In this state, the input circuit writes an expected value, and a logic level is read from the latch circuit. Accordingly, failure of the evaluation wiring can be easily discriminated from other failure.

Semiconductor integrated circuit and evaluation method of wiring in the same

A circuit for data transfer includes a first buffer operating at a first clock frequency, a plurality of second buffers operating at a second clock frequency, and a selector circuit which receives data at the first clock frequency, and supplies the data to a selected one of the first buffer and the second buffers.

Data transfer circuit between different clock regions

A signal transmission system has a response time of a signal transmission line which is set approximately equal to or longer than the length of a transmitted symbol. More specifically, terminal resistance is set larger than the characteristic impedance of the signal transmission line, driver output resistance is set to a large value, or a damping resistor is provided in series with the signal transmission line. With this configuration, signal power can be reduced drastically.

SIGNAL TRANSMISSION SYSTEM FOR TRANSMITTING SIGNALS BETWEEN LSI CHIPS, RECEIVER CIRCUIT FOR USE IN THE SIGNAL TRANSMISSION SYSTEM, AND SEMICONDUCTOR MEMORY DEVICE APPLYING THE SIGNAL TRANSMISSION SYSTEM

Signal transmission system having a timing adjustment circuit

A restoring circuit,, provided for each of the memory blocks,and,, having registers and a selector for selecting one of the present row address and the output of the registers, provides the output of the selector to a word decoder,. The present row address is held in one of the registers. When amplification is started by a sense amplifier,, transfer gates,and,connected between the bit lines BL,and *BL,and the sense amplifier,are turned off to decrease the load of the sense amplifier,, the amplified signal is stored in a buffer memory cell circuit,, and accessing is completed with omitting restoring to the memory cell,. While the memory cell block,is not selected, the data held in the buffer memory cell circuit,is stored into the memory cell row addressed by the content of the selected register. The sense amplifier,has PMOS and NMOS sense amplifiers. The PMOS sense amplifier, having a pair of cross-coupled PMOS transistors and a pair of transfer gates, the potential of the sources of the PMOS transistors being fixed at Vii, operates in a direct sensing mode when the transfer gates are off state, and then functions as a usual PMOS sense amplifier by turning on the transfer gates. Likewise for the NMOS sense amplifier.

Destructive read type memory circuit, restoring circuit for the same and sense amplifier

Timing signal generating circuit, semiconductor integrated circuit device and semiconductor integrated circuit system to which the timing signal generating circuit is applied, and signal transmission system

A logical circuit device has a MOS transistor having a source region, a drain region, a channel region defined between the source region and the drain region, and a gate electrode formed above the channel region, respectively formed on a semiconductor substrate. The amplitude of a voltage applied to the gate electrode necessary for making the channel region conductive is not level throughout the channel region in the width direction. Using such a logical circuit device, flip-flop circuits and storage circuits of a multivalued logic type can be realized.

Logical circuit, flip-flop circuit and storage circuit with multivalued logic

A restoring circuit,provided for each of the memory blocks,and,having registers and a selector for selecting one of the present row address and the output of the registers, provides the output of the selector to a word decoder,The present row address is held in one of the registers. When amplification is started by a sense amplifier,transfer gates,and,connected between the bit lines BL,and *BL,and the sense amplifier,are turned off to decrease the load of the sense amplifier,the amplified signal is stored in a buffer memory cell circuit,and accessing is completed with omitting restoring to the memory cell,While the memory cell block,is not selected, the data held in the buffer memory cell circuit,is stored into the memory cell row addressed by the content of the selected register. The sense amplifier,has PMOS and NMOS sense amplifiers. The PMOS sense amplifier, having a pair of cross-coupled PMOS transistors and a pair of transfer gates, the potential of the sources of the PMOS transistors being fixed at Vii, operates in a direct sensing mode when the transfer gates are off state, and then functions as a usual PMOS sense amplifier by turning on the transfer gates. Likewise for the NMOS sense amplifier.

Growing community of inventors

Kawasaki, Japan

Shigetoshi Wakayama