Hitachi, Ltd.

Hitachi Vlsi Engineering Corp.

Shigetoshi Sakomura

Masamichi Ishihara

Hidetoshi Iwai

Hiroyuki Uchiyama

Ryoichi Hori

Yasushi Takahashi

Kazuyuki Miyazawa

Hisashi Nakamura

Masaya Muranaka

Satoshi Oguchi

Hiromi Matsuura

Yoshihisa Koyama

Hidetomo Aoyagi

Haruo Ii

Takeshi Kizaki

Toshiyuki Sakuta

Kazuya Ito

Toshitugu Takekuma

Yutaka Ito

Toshitsugu Takekuma

Masanori Tazunoki

Wataru Arakawa

Toshitugu Takemuma

Tomoshi Matsumoto, Deceased

A semiconductor memory device is provided which includes a substrate arrangement which is suitable for forming a large number of types of DRAMs having different package specifications, different bit structure and different operating modes. In conjunction with this, the bonding pads are arranged at optimum locations for accommodating the different package types. Various layout arrangements are also provided to minimize space and to improve access time. Additional features are provided, including improved output buffer circuitry, protection circuitry and testing methods to facilitate operation of the semiconductor memory device.

Semiconductor memory device with improved substrate arrangement to

A dynamic RAM provided with a data retention mode intended for low power consumption is provided. In the data retention mode, the current supply capabilities of voltage generation circuits which generate decreased voltage, increased voltage, reference voltage, etc., are limited in the range in which information retention operation in memory cells can be maintained, and the number of selected memory mats in the data retention mode is increased with respect to that of memory mats selected in the normal read/write mode and refresh mode. Special modes such as the data retention mode are set by combining an address strobe signal and other control signals and dummy CBR refresh is executed to release the special mode.

Special mode control method for dynamic random access memory

A semiconductor memory device is provided which includes a plurality of data lines, at least one redundant data line, one common data line, a plurality of column switches installed between the plurality of data lines and the redundant data line and one common data line, and a column decoder for controlling the plurality of column switches. The column decoder operates to turn the column switch on. The column switch is connected to a plurality of data lines, excluding any defective data and redundant data lines during the test mode state.

Semiconductor memory device

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Ohme, Japan

Shigetoshi Sakomura