Tokyo Electron Limited

Tohoku University

Shigetoshi Hosaka

Junichi Koike

Hitoshi Itoh

Koji Neishi

Kenji Matsumoto

Yumiko Kawano

Hidenori Miyoshi

Masayuki Tomoyasu

Hiroshi Sato

Tomihiro Yonenaga

Hiroshi Kobayashi

Yuichi Wada

Hatsuo Osada

Taro Komiya

Tetsuya Yano

A film forming method performs a film forming process on a target object having on a surface thereof an insulating layer. The film forming method includes a first thin film forming step of forming a first thin film containing a first metal, an oxidation step of forming an oxide film by oxidizing the first thin film, and a second thin film forming step of forming a second thin film containing a second metal on the oxide film.

Film forming method and processing system

A film forming method is disclosed in which a thin film comprising manganese is formed on an object to be processed which has, on a surface thereof, an insulating layer constituted of a low-k film and having a recess. The method comprises a hydrophilization step in which the surface of the insulating layer is hydrophilized to make the surface hydrophilic and a thin-film formation step in which a thin film containing manganese is formed on the surface of the hydrophilized insulating layer by performing a film forming process using a manganese-containing material gas on the surface of the hydrophilized insulating layer. Thus, a thin film comprising manganese, e.g., an MnOx film, is effectively formed on the surface of the insulating layer constituted of a low-k film, which has a low dielectric constant.

Film forming method, pretreatment device, and processing system

A seed layer is formed on a surface of an insulating film and along a recess of the insulating film, and after a copper wiring is buried in the recess, a barrier film is formed, and an excessive metal is removed from the wiring. On a surface of a copper lower layer conductive path exposed at the bottom of the recess, a natural oxide of the copper is reduced or removed. On a substrate from which the natural oxide is reduced or removed, the seed layer, composed of a self-forming barrier metal having oxidative tendency higher than that of copper or an alloy of such metal and copper, is formed. The substrate is heated after burying copper in the recess. Thus, a barrier layer is formed by oxidizing the self-forming barrier metal. An excessive portion of the self-forming barrier metal is deposited on a surface of the buried copper.

Semiconductor device manufacturing method, semiconductor manufacturing apparatus and storage medium

The present invention provides a gas process apparatus that realizes uniform exhaust without depending on process conditions, a gas process chamber that constitutes the gas process apparatus, a baffle plate mounted on the gas process chamber, a method of producing the baffle plate, and an apparatus for producing the baffle plate. The baffle plate of the present invention serves as a partition between a process space in which a chemical process is carried out with a supplied gas, and a duct that is adjacent to the process space and functions to discharge exhaust gas generated as a result of the chemical process. In accordance with the difference between the pressures on both sides of the baffle plate, which difference varies depending on the location on the baffle plate, the baffle holes are disposed on a plurality of locations on the baffle plate.

Baffle plate, apparatus for producing the same, method of producing the same, and gas processing apparatus containing baffle plate

The multilevel interconnection forming method of the present invention comprises the following. A metal film containing aluminum is deposited on an insulating film of a substrate, and the metal film is patterned, to form a wiring layer of a first layer. An interlayer dielectric film forming part of the first layer is formed on an entire surface of the substrate, such that the interlayer dielectric film covers the wiring layer from upside. A hole is formed at a predetermined position of the interlayer dielectric film such that the hole reaches the wiring layer of the first layer. Aluminum is selectively deposited and filled into the hole by a CVD method, such that the aluminum is filled at a volume ratio smaller than 100% with respect to the hole. An active metal film is formed on an entire upper surface of an interlayer dielectric film including the hole filled with the aluminum. A metal layer containing aluminum is formed on the active metal film. The metal layer is made to flow into the hole by reflowing, to completely fill the hole and to planarize the surface of the metal layer. The metal layer is subjected to be patterned, to form a wiring layer of a second layer, after the surface of the metal layer is planarized by the reflowing.

Multilevel interconnection forming method for forming a semiconductor

Growing community of inventors

Nirasaki, Japan

Shigetoshi Hosaka