Murata Manufacturing Co., Ltd.

Shigetoshi Hayashi

Tomoya Yokoyama

Takako Sato

Hirokazu Yazaki

Jun Endo

Takashi Kihara

Shinichiro Kawada

Yoshihiro Yamaguchi

Yutaka Ishiura

Fumiya Isono

Seishiro Goto

Akihiro Ieda

Yusuke Nakamura

Akio Fujita

Yoshiyuki Yamakawa

A piezoelectric actuator that includes a multilayer body, a low-potential outer electrode, and a high-potential outer electrode. The multilayer body includes multiple alternately stacked piezoelectric ceramic layers and planar electrodes. The planar electrodes include low-potential planar electrodes electrically connected to the low-potential outer electrode and high-potential planar electrodes electrically connected to the high-potential outer electrode. The planar electrode positioned most outwardly on the side of a first main surface of the multilayer body is a low-potential planar electrode. The inner surface of this low-potential planar electrode contacts the &#x2212; side of polarization in an active region, and the outer surface of this low-potential planar electrode is exposed on an outside of the multilayer body. On the side of a second main surface of the multilayer body, a high-potential planar electrode is not exposed on the outside of the multilayer body.

Piezoelectric actuator and drive method therefor

Disclosed is a piezoelectric film sensor including an insulating substrate having a first electrode formed on at least one main surface thereof, a piezoelectric film which has a first main surface and a second main surface and in which the first main surface is provided on the first electrode side, and a conductive thin film member provided on the second main surface side. The piezoelectric film sensor is characterized in that the first main surface is disposed on a pressing surface side.

Piezoelectric film sensor and holding state detecting device

Provided is a laminated-type inductance device capable of reducing the number of layers for sandwiching a non-magnetic body layer and enhancing direct-current superposition characteristics without intentionally providing a space. In a conductive pattern, portions of the outer circumferential section thereof adjacent to end surface electrodes are respectively recessed toward the inside of the pattern when viewed from above. In other words, line widths are narrower at the above portions. Further, non-magnetic paste is formed between the end surface electrode and the outer circumferential section of the conductive pattern at each of the portions where the line width is narrower. By applying the non-negative paste in a space between the conductive pattern and the end surface electrode, the portion where the non-magnetic paste is applied has the same function as in a case where the non-magnetic ferrite layer is inserted therein.

Laminated-type inductance device

Provided is a multilayer substrate that can prevent generation of cracks caused by stress generated due to a difference between the coefficient of linear expansion of electrode pads and that of a ceramic material. An electrode pad arranged on a layer below an outermost component mounting electrode pad has a larger area than an area of the component mounting electrode pad. Similarly, an electrode pad arranged on a layer below a component mounting electrode pad has a larger area than an area of the component mounting electrode pad, an electrode pad arranged on a layer below a component mounting electrode pad has a larger area than an area of the component mounting electrode pad, and an electrode pad arranged on a layer below a component mounting electrode pad has a larger area than an area of the component mounting electrode pad.

Multilayer substrate

In a laminated inductor element, outer electrodes and terminal electrodes are electrically connected by via holes, internal wiring lines, and end surface electrodes. The via holes on an upper surface side are provided immediately under the outer electrodes and in a non-magnetic ferrite layer. The via holes on a lower surface side are provided immediately above the terminal electrodes and in a non-magnetic ferrite layer. Since outermost layers are defined by the non-magnetic ferrite layers, a parasitic inductance is not increased, even if the outermost layers are provided with the via holes. In this case, the internal wiring lines are not routed on a surface of the element. Therefore, there is no complication of a wiring pattern, and it is possible to prevent an increase in a mounting area of the element.

Laminated inductor element and manufacturing method thereof

Growing community of inventors

Nagaokakyo, Japan

Shigetoshi Hayashi