Mitsubishi Denki Kabushiki Kaisha

Renesas Technology Corp.

Ryoden Semiconductor System Engineering Corporation

Other

Renesas Electronics Corporation

Ion Engineering Research Institute Corporation

Shigeto Maegawa

Shigenobu Maeda

Toshiaki Iwamatsu

Takashi Ipposhi

Yasuo Yamaguchi

Yuuichi Hirano

Takuji Matsumoto

Hirotada Kuriyama

Yasuo Inoue

Motomu Ukita

Kyozo Kanamoto

Yoshinori Okumura

Shuichi Ueno

Mikio Tsujiuchi

Shoichi Miyamoto

Kazuhito Tsutsumi

Koji Nii

Yoshiyuki Ishigaki

Toshiaki Tsutsumi

Hidekazu Yamamoto

Hisayuki Nishimura

Il-Jung Kim

Kiyohiko Sakakibara

Nobuyoshi Hattori

Toshihiko Hirose

Hideki Naruoka

Hiroshi Kawashima

Tadashi Nishimura

Tatsuhiko Ikeda

Kazunobu Ohta

Yuichi Hirano

Il Jung Kim

Masanobu Kohara

Takashi Eura

Natsuro Tsubouchi

In a semiconductor device, a body thick film transistor and a body thin film transistor having a different body film thickness are formed on the same SOI substrate (silicon support substrate, buried oxide film and silicon layer). The body film is formed to be relatively thick in the body thick film transistor, which has a recess structure where the level of the surface of the source/drain regions is lower than the level of the surface of the body region, and thus, the SOI film in the source/drain regions is formed to be as thin as the SOI film in the body thin film transistor. On the other hand, the entirety of the SOI film is formed to have a relatively thin film thickness in the body thin film transistor. In addition, the source/drain regions are formed to penetrate through the silicon layer.

Semiconductor device and manufacturing method for the same

The present invention provides a semiconductor device capable of suppressing a body floating effect, and a manufacturing method thereof. A semiconductor device having an SOI structure includes a silicon substrate, a buried insulating layer formed on the silicon substrate, and a semiconductor layer formed on the buried insulating layer. The semiconductor layer has a body region of a first conduction type, a source region of a second conduction type and a drain region of the second conduction type, and a gate electrode is formed on the body region between the source region and the drain region via a gate oxide film. The source region includes an extension layer of the second conduction type, and a silicide layer which makes contact with the extension layer at its side face, and a crystal defect region is formed on a region of a depletion layer generated in a boundary portion between the silicide layer and the body region.

Semiconductor device having an SOI structure, manufacturing method thereof, and memory circuit

A partial oxide film with well regions formed therebeneath isolates transistor formation regions in an SOI layer from each other. A p-type well region is formed beneath part of the partial oxide film which isolates NMOS transistors from each other, and an n-type well region is formed beneath part of the partial oxide film which isolates PMOS transistors from each other. The p-type well region and the n-type well region are formed in side-by-side relation beneath part of the partial oxide film which provides isolation between the NMOS and PMOS transistors. A body region is in contact with the well region adjacent thereto. An interconnect layer formed on an interlayer insulation film is electrically connected to the body region through a body contact provided in the interlayer insulation film. A semiconductor device having an SOI structure reduces a floating-substrate effect.

Semiconductor device, method of manufacturing same and method of designing same

An isolation insulating film () of partial-trench type is selectively formed in an upper surface of a silicon layer (). A power supply line () is formed above the isolation insulating film (). Below the power supply line (), a complete isolation portion () reaching an upper surface of an insulating film () is formed in the isolation insulating film (). In other words, a semiconductor device comprises a complete-isolation insulating film which is so formed as to extend from the upper surface of the silicon layer () and reach the upper surface of insulating film () below the power supply line (). With this structure, it is possible to obtain the semiconductor device capable of suppressing variation in potential of a body region caused by variation in potential of the power supply line.

Semiconductor device and method of manufacturing the same

A contact connected to a word line is formed on a gate electrode of an access transistor of an SRAM cell. The contact passes through an element isolation insulating film to reach an SOI layer. A body region of a driver transistor and that of the access transistor are electrically connected with each other through the SOI layer located under the element isolation insulating film. Therefore, the access transistor is in a DTMOS structure having the gate electrode connected with the body region through the contact, which in turn is also electrically connected to the body region of the driver transistor. Thus, operations can be stabilized while suppressing increase of an area for forming the SRAM cell.

Semiconductor memory device

The semiconductor device has a silicon layer (SOI layer) () formed through a silicon oxide film () on a support substrate (). A transistor (T) is formed in the SOI layer (). The wiring () is connected with a source of the transistor (T) through a contact plug (). A back metal () is formed on an under surface (back surface) of the support substrate () and said back metal () is connected with the wiring () through a heat radiating plug (). The contact plug (), the heat radiating plug () the wiring () and the back metal () is made of a metal such as aluminum, tungsten and so on which has a higher thermal conductivity than that of the silicon oxide film () and the support substrate ().

Semiconductor device with effective heat-radiation

There is provided a semiconductor device which is formed on a semiconductor substrate and allows effective use of the feature of the semiconductor substrate, and there is also provided a method of manufacturing the same. An N-channel MOS transistor including a P-type body layer (), and a P-type active layer () for body voltage application which is in contact with the P-type body layer () are formed on an SOI substrate which is formed to align a &#x3c;110&#x3e; crystal direction of a support substrate () with a &#x3c;100&#x3e; crystal direction of an SOI layer (). A path connecting the P-type body layer () and the P-type active layer () for body voltage application is aligned parallel to the &#x3c;100&#x3e; crystal direction of the SOI layer (). Since hole mobility is higher in the &#x3c;100&#x3e; crystal direction, parasitic resistance (Ra, Rb) can be reduced in the above path. This speeds up voltage transmission to the P-type body layer () and improves voltage fixing capability in the P-type body layer ().

Semiconductor MIS transistor formed on SOI semiconductor substrate

In a semiconductor device, a gate electrode, an impurity diffused region, a body potential fixing region, a first insulator, and a dummy gate electrode are provided on top of an SOI substrate consisting of an underlying silicon substrate, a buried insulator, and a semiconductor layer. The impurity diffused region is a region formed by implanting an impurity of a first conductivity type into the semiconductor layer around the gate electrode. The body potential fixing region is a region provided in the direction of an extension line of the length of the gate electrode and implanted with an impurity of a second conductivity type. The first insulator is formed at least in the portion between the body potential fixing region and the gate electrode. The dummy gate electrode is provided on the first insulator between the body potential fixing region and the gate electrode.

Semiconductor device having SOI structure and method for manufacturing the same

A Schottky junction is formed at the connection between an SOI layer and a contact (namely, under an element isolation insulating film) without forming a Pregion with a high impurity concentration thereat. The surface of a body contact is provide with a barrier metal. A silicide is formed between the body contact and the SOI layer as a result of the reaction of the barrier metal and the SOI layer.

Semiconductor device including a contact connected to the body and method of manufacturing the same

Semiconductor memory device and method of manufacturing the same

While improving the frequency characteristics of a decoupling capacitor, suppressing the voltage drop of a source line and stabilizing it, the semiconductor device which suppressed decline in the area efficiency of decoupling capacitor arrangement is offered. Decoupling capacitors DMand DMare connected between the source line connected to the pad for high-speed circuits which supplies electric power to circuit block C, and the ground line connected to a ground pad, and the capacitor array for high-speed circuits is formed. A plurality of decoupling capacitor DMare connected between the source line connected to the pad for low-speed circuits which supplies electric power to circuit block C, and the ground line connected to a ground pad, and the capacitor array for low-speed circuits is formed. Decoupling capacitor DMdiffers in the dimension of a gate electrode from DM

Semiconductor device

Provided are a thin-film transistor formed by connecting polysilicon layers having different conductivity types with each other which prevents occurrence of inconvenience resulting from diffusion of impurities and a method of fabricating the same. A drain (), a channel () and a source () are integrally formed on a surface of a second oxide film () by polysilicon. The drain () is formed to be connected with a pad layer () (second polycrystalline semiconductor layer) through a contact hole () which is formed to reach an upper surface of the pad layer (). The pad layer () positioned on a bottom portion of the contact hole () (opening) is provided with a boron implantation region BR.

Thin-film transistor and method of fabricating the same

A partial oxide film () with well regions formed therebeneath isolates transistor formation regions in an SOI layer () from each other. A p-type well region () is formed beneath part of the partial oxide film () which isolates NMOS transistors from each other, and an n-type well region () is formed beneath part of the partial oxide film () which isolates PMOS transistors from each other. The p-type well region () and the n-type well region () are formed in side-by-side relation beneath part of the partial oxide film () which provides isolation between the NMOS and PMOS transistors. A body region is in contact with the well region () adjacent thereto. An interconnect layer formed on an interlayer insulation film () is electrically connected to the body region through a body contact provided in the interlayer insulation film (). A semiconductor device having an SOI structure reduces a floating-substrate effect.

Growing community of inventors

Tokyo, Japan

Shigeto Maegawa