Nec Corporation

Shigeto Inui

Yasuhiko Hagihara

A latch conversion circuit which is to be added to a basic logic circuit to obtain a latch circuit having an extremely small through delay amount is prepared in advance. Moreover, provided is means for obtaining a latch circuit position whereat the shifting of the clock edge, such as skew or jitter, can be absorbed to the maximum extent possible, and for forming a latch circuit by adding the latch conversion circuit to the basic logic circuit located at the obtained point. Accordingly, a latch circuit which is not, to the extent possible, affected by skew or jitter can be designed.

Logic circuit, logic circuit design method, logic circuit design system, and logic circuit design program

In a dual rail domino circuitusing a combination of a domino circuitfor outputting positive logic and a domino circuitfor outputting negative logic, an ANDand a NANDas members for simultaneously fixing an output of the domino circuitand an output of the domino circuitat a low level in an evaluation phase are provided, and a logical AND of a gating control signal and an input signal is inputted to the domino circuitand a logical NOT of the logical AND of the gating control signal and the input signal is inputted to the domino circuit

Dual rail domino circuit and logic circuit

A higher-radix type divider is provided which is capable of obtaining a quotient at a high speed by performing a scaling on a divisor and by representing a partial remainder in a redundant binary notation. The divider for obtaining the quotient by referring to the divisor and dividend normalized respectively so as to satisfy a range of &#xbd;or more and less an &#xbd;(k being a positive integer) and to a length of bits, out of all bits of the partial remainder, defined by a radix for operations and a maximum number of digits, is provided with a scaling factor generating section, a multiplying section, a divisor tripled-number generating section and a repetitive operating section.

Divider

A high-speed dynamic logic circuit having a high tolerance to noise includes pMOS and nMOS transistors constructing a buffer, which is connected to an internal dynamic node, for driving an output terminal. Only the pMOS transistor, which operates in an evaluation cycle, is connected to the dynamic node. The nMOS transistor is driven by a signal that is the inverse of a precharge signal. A weak latch, or an nMOS transistor of minimum size driven by the dynamic node, is connected to the output terminal as a leakage compensation circuit.

Dynamic logic circuit

A carry look ahead addition device includes a carry generation/propagation term generator which receives input of two numbers each having a length of n (positive integer) bits and generates the carry generation term and the carry propagation term for each bit, a carry generator which generates a carry for each bit based on the carry input and the carry generation term and the carry propagation term from the carry generation/propagation term generator, and a sum generator. The carry generator receives the carry input and, at the same time, the carry generation term and the carry propagation term are generated at the carry generation/propagation term generator. The carry generator deems the carry input as the carry generation term at the bit immediately below the least significant bit (Bit -1) and the carry propagation term at the Bit -1 to be 0 for processing without a carry input for n+1 bits so as to generate a carry having a length of n+1 bits.

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Tokyo, Japan

Shigeto Inui