Mitsubishi Electric Corporation

Shigeto Honda

Kaoru Motonami

Atsushi Narazaki

Tetsuo Takahashi

Hidenori Fujii

Kazunari Nakata

Ryoichi Fujii

Tetsuya Nitta

Yuji Ebiike

Fumihito Masuoka

Takahiro Nakatani

Yuki Haraguchi

Tomoya Hirata

Ayumu Onoyama

According to the present disclosure, a semiconductor apparatus comprises a first gate electrode; a second gate electrode connected in parallel with the first gate electrode; a control circuit connected to the first gate electrode and the second gate electrode and configured to control gate voltages; and a coil connected between the second gate electrode and the control circuit.

Semiconductor apparatus

A transistor and a diode are formed on a common semiconductor substrate; the semiconductor substrate has a transistor region and an outer peripheral region surrounding it; the transistor region is divided into a plurality of channel regions and a plurality of non-channel regions by a plurality of gate electrodes each having a stripe shape; each of the plurality of non-channel regions has a first semiconductor layer, a second semiconductor layer, a third semiconductor layer, a fifth semiconductor layer, a first electrode, and a second electrode; the third semiconductor layer and the fifth semiconductor layer are electrically connected to the second electrode via a contact hole; and the fifth semiconductor layer is selectively provided not to be in contact with an impurity layer of a first conductivity type that is provided in the outer peripheral region and defines a boundary with a cell region.

Semiconductor device

A semiconductor substrate has a transistor region, a diode region, and an outer peripheral region. The transistor region is divided into a plurality of transistor unit cell regions by a plurality of gate electrodes each having a stripe shape, and the diode region is divided into a plurality of diode unit cell regions by the plurality of gate electrodes. Each of the plurality of transistor unit cell regions has a third semiconductor layer of a first conductivity type provided on a first main surface side of the semiconductor substrate, a fourth semiconductor layer of a second conductivity type selectively provided on an upper layer part of the third semiconductor layer, and a fifth semiconductor layer. The fifth semiconductor layer is provided to be in contact with an impurity layer of the first conductivity type provided in the outer peripheral region, or to enter the impurity layer.

A semiconductor device in which a transistor and a diode are formed on a common semiconductor substrate is provided. The semiconductor substrate includes a transistor region in which a transistor is formed and a diode region in which a diode is formed. At least one first electrode on a second main surface side of the transistor region and at least one second electrode on a second main surface side of the diode region are made of different materials.

The semiconductor device according to the present invention includes: an n-type semiconductor substrate; a p-type anode layer provided in a front surface of the n-type semiconductor substrate; an anode electrode provided on the p-type anode layer; and a wire connected to the anode electrode, the p-type anode layer includes: a p-type anode layer disposed to include a position right under a portion where the wire is connected; and a p-type anode layer disposed to exclude the position right under the portion where the wire is connected, and an impurity concentration of the p-type anode layer is higher than an impurity concentration of the p-type anode layer.

Semiconductor device and manufacturing method thereof

In a semiconductor device according to the present invention, an electrode layer and a recessed part are formed on a surface of a semiconductor substrate. Further, in the semiconductor substrate, a RESURF layer that is in contact with a bottom surface of the recessed part and the electrode layer is formed. In addition, an insulating film is formed on an upper surface of the semiconductor substrate so as to fill the recessed part. Moreover, a field plate electrode is formed on the insulating film above the recessed part.

High breakdown voltage semiconductor device having a resurf layer

A semiconductor device includes a semiconductor substrate having a collector layer in which the carrier concentration is maximized at a carrier concentration peak position that is 1 &#x3bc;m or more from a surface of the semiconductor substrate. The semiconductor device further includes a collector electrode formed in contact with a surface of the collector layer.

Semiconductor device and method for manufacturing a semiconductor device having a maximal carrier concentration at multiple carrier concentration peak positions

A power semiconductor device according to the present invention, which has a termination structure in which a field plate is provided on an insulating film filled in a recessed region formed in a semiconductor substrate and includes a plurality of unit cells connected in parallel, includes: a gate wiring region in which gate wiring electrically connected to each gate electrode of the plurality of unit cells is provided; and a gate pad region electrically connected to the gate wiring region, wherein the gate wiring region is disposed on the insulating film filled in a recessed region formed in the semiconductor substrate.

Power semiconductor device

A method of manufacturing a power semiconductor device according to the present invention includes the steps of: (a) forming a silicon nitride film on a semiconductor substrate; (b) after the step (a), forming a ring-shaped trench along a peripheral portion of the semiconductor substrate; (c) forming a first silicon oxide film on an inner surface of the trench; (d) after the step (c), forming a second silicon oxide film on an entire surface of the semiconductor substrate to bury the trench; (e) planarizing the second silicon oxide film by using the silicon nitride film as a stopper; and (f) forming a third silicon oxide film in a region in which the silicon nitride film is removed.

Power semiconductor device and method of manufacturing the same

A passivation film having a predetermined width from an outer peripheral end portion toward an inner side and extending along the outer peripheral end portion is formed on a front surface of a semiconductor substrate. An outer peripheral end surface orthogonal to the front surface and a rear surface is formed by grinding the outer peripheral end portion of the semiconductor substrate. A thickness of the semiconductor substrate is reduced to a predetermined thickness by grinding the rear surface. The ground rear surface is etched by discharging a mixed acid onto the rear surface while rotating the semiconductor substrate with the rear surface facing upward, to remove a fracture layer. Thereby, chipping or cracking of the semiconductor substrate is suppressed.

Method of manufacturing semiconductor device

A semiconductor device includes a base layer that has a first conductivity type, a source layer that is formed on the base layer and has a second conductivity type, and an insulating film that is formed on the source layer. The semiconductor device further includes a plurality of gate structures that penetrate the base layer, and a plurality of conductive parts that penetrate the insulating film and the source layer and electrically connect the source layer and the base layer to each other. The gate structures are formed in a stripe shape in plan view. Parts in which the conductive portion is connected to the base layer are formed in a stripe shape in plan view, and are formed between the gate structures. Further, a dimension of the part in which the source layer and the base layer are in contact with each other between the gate structure and the conductive portion is 0.36 &#x3bc;m or more.

Growing community of inventors

Tokyo, Japan

Shigeto Honda