Sony Corporation

Sony Semiconductor Solutions Corporation

Nippon Scitec Co., Ltd.

Eiichi Saita

Shigetaka Mori

Shintaro Okamoto

Yohei Hiura

Nobutoshi Fujii

Kenichi Murata

Akihiko Mori

Hiroyuki Kawashima

Koichiro Zaitsu

Shuji Manda

Naohiko Kimizuka

Shinichi Miyake

Keiji Ohshima

Keiichi Nakazawa

Hirofumi Yamashita

Naoki Saka

Junpei Yamamoto

Hidetoshi Oishi

Shinji Nakagawa

Hitoshi Okano

Takuma Matsuno

Katsuhisa Kugimiya

Yusuke Kohyama

Yasushi Hamamoto

Tomoki Kambe

Ryo Ogata

Tatsuki Miyaji

Yui Yuga

An imaging device according to an embodiment of the present disclosure includes: a first substrate including a sensor pixel that performs photoelectric conversion; a second substrate including a pixel circuit that outputs a pixel signal on a basis of electric charges outputted from the sensor pixel; and a third substrate including a processing circuit that performs signal processing on the pixel signal. The first substrate, the second substrate, and the third substrate are stacked in this order, and a concentration of electrically-conductive type impurities in a region on side of the first substrate is higher than a concentration of electrically-conductive type impurities in a region on side of the third substrate, in at least one or more semiconductor layers in which a field-effect transistor of the pixel circuit is provided.

Imaging device

There is provided a solid-state imaging device including: a first semiconductor layer including a photoelectric converter and an electric charge accumulation section for each pixel, the electric charge accumulation section in which a signal electric charge generated in the photoelectric converter is accumulated; a pixel separation section that is provided in the first semiconductor layer, and partitions a plurality of the pixels from each other; a second semiconductor layer that is provided with a pixel transistor and is stacked on the first semiconductor layer, the pixel transistor that reads the signal electric charge of the electric charge accumulation section; and a first shared coupling section that is provided between the second semiconductor layer and the first semiconductor layer, and is provided to straddle the pixel separation section and is electrically coupled to a plurality of the electric charge accumulation sections.

Solid-state imaging device

Provided is a semiconductor device, a measurement device, a measurement method, and a semiconductor system that enable accurate measurement of the plasma induced damage (PID) effect on a small scale. The semiconductor device includes an NMOSFET whose gate is connected to an antenna part that functions as an antenna in a plasma process and a PMOSFET that controls the connection between the NMOSFET and a ring oscillator. The semiconductor device is provided with a test element group (TEG) that includes an NMOSFET whose gate is connected to an antenna part that functions as an antenna in a plasma process and a PMOSFET that controls the connection between the NMOSFET and a ring oscillator.

Semiconductor device, measurement device, measurement method, and semiconductor system for plasma induced damage (PID) measurement

The present disclosure relates to a semiconductor integrated circuit and a signal processing method that can improve measurement accuracy. Pulses subjected to pulse generation and disconnection control by a control circuit are supplied to a pulse distribution circuit and a CP circuit. The pulse distribution circuit divides one pulse into two or more pulses that do not overlap each other, and supplies the pulses to a CBCM circuit. The CBCM circuit is configured by connecting a capacitance element to be measured to the output of a measurement core circuit called a pseudo inverter. The CP circuit inputs, to the gate electrode, pulses that cause a channel of a non-measurement MISFET to change from the accumulation state to the inverted state, and monitors, from the substrate side, a CP current flowing through a trap acting as a recombination center of the gate insulating film and the semiconductor substrate interface. The present disclosure can be applied to, for example, a semiconductor integrated circuit for evaluating the characteristics of the gate insulating film of the MISFET.

Semiconductor integrated circuit and signal processing method

The present disclosure relates to a semiconductor device, an operation method of a semiconductor device, and a manufacturing method of a semiconductor device which are capable of minimizing influence of a gate length variation on a circuit characteristic and increasing a good product ratio (yield) in a product sorting test. A ring oscillator configured such that the plurality of inverters is connected in a ring-like form, and gate capacitors of the transistors are connected to respective output terminals of the plurality of inverters as a load capacitor outputs an oscillating signal, the ring oscillator is configured with a plurality of transistors having the same gate length, and at least two or more ring oscillators including a plurality of transistors having different gate lengths are configured. At the time of product test, the gate length is calculated on the basis of frequencies of oscillating signals of a plurality of ring oscillators, and a back bias is applied in accordance with a correction value corresponding to the calculated gate length, and an operation is performed. The present disclosure can be applied to semiconductor devices.

Semiconductor device, operation method of semiconductor device, and manufacturing method of semiconductor device

A method of manufacturing a semiconductor device, includes: forming an insulating film on a first surface of a semiconductor substrate; and forming a hydrogen supply film on a second surface facing the first surface of the semiconductor substrate, the hydrogen supply film containing one or more of silicon oxide, TEOS, BPSG, BSG, PSG, FSG, carbon-containing silicon oxide, silicon nitride, carbon-containing silicon nitride, and oxygen-containing silicon carbide.

Semiconductor device and method of manufacturing the same

The present invention relates to a process for producing gelatinized grain for food or food processing material without steaming or boiling. The present invention comprises adjusting the water content of the grain before puffing to 40% or less, puffing the grain at 100.degree. C., further adding water to the puffed grain, and then coarsely pulverizing the grain, thereby producing coarsely pulverized porous grain. According to the present invention, the coarsely pulverized porous grain having a good crispness as well as a homogeneous water absorption and easy handling, can be obtained.

Process for producing pregelatinized grain

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Kanagawa, Japan

Shigetaka Mori