Fujitsu Corporation

Fujitsu Semiconductor Limited

Fujitsu Microelectronics Limited

Shigetaka Asano

Masaru Sawada

Kazufumi Komura

Tohru Yasuda

Yoshitaka Nakata

Takayoshi Nakamura

Keiichi Fujimura

Nobuyoshi Nakaya

Katsumi Furukawa

Kanta Yamamoto

Kazuyoshi Kikuta

Hirohisa Nishiyama

A semiconductor device includes a monitor including a first element coupled between a first power supply line and a second power supply line, and a load for increasing a load value between the first element and the first power supply line or the second power supply line, and a determination unit which determines an operating state of the first element based on an output of the monitor.

Semiconductor device and operation monitoring method for semiconductor device

A timing controller includes a controller that controls an operation timing of a controlled unit, and a setting unit that associates a timing obtained by dividing a setting of the operation timing into a plurality of timings, each timing having an identification number, and sets the control unit so that an offset period based on the associated timing is added to the operation timing of the controlled unit.

Timing controller, timing control method, and timing control system

Herein disclosed is a variable delay circuit, including a first delay portion that delays an input signal; an output portion; and a variable impedance portion provided coupled between the first delay portion and an the output portion.

Variable delay circuit, variable delay device, and VCO circuit

A delay adjusting circuit including a delay part in which delay elements of n+1 (n&#x2267;2) stages are connected to each other in series, a first phase comparator for detecting whether a first edge that is a transition edge of a signal of an n&#x2212;1-th stage of the delay part from a first logic level to a second logic level advances from a first reference signal edge that is a transition edge of a first reference signal from the first logic level to the second logic level, a second phase comparator for detecting whether a second edge that is a transition edge of a signal of an n+1-th stage of the delay part from the first logic level to the second logic level delays from the first reference signal edge, and a delay element adjusting part that corrects a second reference signal so that the first edge advances from the first reference signal edge in the first phase comparator and the second edge delays from the first reference signal edge in the second phase comparator, and that outputs a reference bias signal for adjusting delay times of the delay elements of the delay part.

Delay adjusting circuit and control method of the same

An object of the invention is to provide a semiconductor device and an adjusting method for a semiconductor device wherein power source noises and noises radiated as radio waves can be reduced and power source noises inside the semiconductor device can be cut. The open stub OSis formed in the upper wiring layer of the semiconductor device. The stub length Lis set to a length of &#xbc; of the wavelength of the known frequency containing peak components of noises. The noise receiving part ATis disposed adjacent to the open stub OS. The open stub OSis connected to the power source wiringby an interlayer wiring. The noise receiving part ATis biased to a ground potential. The basic wave component and odd-number harmonic waves of noises that are generated from the PLL circuitand propagate (the arrow Yof FIG.) in the power source wiringare reflected (arrow Yof FIG.) by the open stub OSso as to return to the PLL circuit, and do not reach the filter circuit

Semiconductor device and adjusting method for semiconductor device

A semiconductor for suppressing power supply resonance caused by the external noise and preventing fluctuation of the power supply voltage. The semiconductor device includes first and second power supply wires for supplying power supply voltages, a variable capacitor circuit connected between the first and second power supply wires, a monitor circuit for detecting the fluctuation of the power supply voltage and generating an output signal indicating the detection thereof, and a controller for changing the capacitance value of the variable capacitor circuit based on the output signal of the monitor circuit.

Semiconductor device

A delay circuit, including: a plurality of first delay units coupled in series and each configured to generate a delay time that is approximately double a unit delay time; a second delay unit configured to generate the unit delay time and coupled to a last stage of the plurality of first delay units; and a selector configured to select either an output signal of the last stage of the plurality of first delay units or an output signal of the second delay unit, wherein an external input signal is input to the first delay unit and to each second delay unit, and the first delay unit and the second delay unit each include a switch circuit configured to output with a delay either an output signal of a previous stage delay unit or the external input signal.

Delay circuit

An analog signal control method for accurately controlling an analog signal irrespective of a latency. The analog signal control method includes the steps of converting the analog signal to a digital signal, performing an arithmetic processing of the digital signal to generate a control signal for controlling the analog signal, delaying the analog signal corresponding to a latency caused by the generation of the control signal to generate a delayed analog signal, and controlling the delayed analog signal in accordance with the control signal.

Analog signal control method, analog signal controller, and automatic gain controller

A device for inhibiting power supply voltage fluctuation that is caused by fluctuation of a load current generated by a load circuit. The device includes a current consumption circuit, a data generation circuit, and a D/A converter. The current consumption circuit is connected to a power supply and the load circuit to generate a consumption current that flows parallel to the load current of the load circuit. The data generation circuit controls the consumption current of the current consumption circuit in order to inhibit fluctuation of an output current of the power supply, which is the sum of the load current and the consumption current, when the load current rises and when the consumption current falls. The D/A converter converts the digital signal to an analog signal and provides the analog signal to the current consumption circuit.

Device and method for inhibiting power fluctuation

A power fluctuation inhibiting device for effectively inhibiting fluctuation of power supply voltage that is supplied to internal circuits. The inhibiting device includes a power fluctuation measuring circuit for measuring peaks in the fluctuation of the power supply voltage produced when the internal circuits are operated. A clock signal control circuit adjusts phases of clock signals provided to respective ones of the internal circuits in accordance to the peak measuring result to substantially offset the fluctuation peaks produced when the internal circuits are operated.

A PLL circuit having a wide oscillation frequency range for reducing a jitter. The PLL circuit including a phase comparator for generating a phase difference signal by comparing a phase of a reference signal with a phase of a comparison signal. An oscillator generates an oscillation frequency signal having an oscillation frequency according to a control signal having a current corresponding to the phase difference signal. A detection circuit generates a detection signal by detecting the current of the control signal. A signal generation circuit generates a signal for changing the oscillation frequency of the oscillator such that the current of the control signal is within a predetermined range in accordance with the detection signal.

Phase locked loop circuit having a wide oscillation frequency range for reducing jitter

A servo controller for correcting a read position of a head when reading data recorded on a recording medium. In accordance with the amplitude ratio of data signals read from each segment of a servo section defined on a recording medium, the servo controller generates an AGC signal corresponding to the next segment before reading the next segment. The data signal read from a phase detection segment of the servo section is amplified to an amplitude greater than the predetermined determination range. The amplified data signal is converted to a two-value digital signal in accordance with the determination range. The phase used during servo control is calculated in accordance with the digital signal.

Servo controller and servo control method

A data reading unit reads analog data stored on a recording medium and converts the analog data to a digital signal synchronously with a clock signal. A waveform equalizer shapes the digital signal using a coefficient. The waveform equalizer also optimizes the coefficient synchronously with the clock signal using an intensity parameter. The waveform equalizer includes a control unit for setting an initial value of the intensity parameter and dynamically adjusting the intensity parameter. The data reader also includes a PLL circuit for generating the clock signal. The PLL circuit may generate the clock signal using a second intensity parameter. The PLL circuit includes a control unit for dynamically altering the second intensity parameter.

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Kasugai, Japan

Shigetaka Asano