Matsushita Electric Industrial Co., Ltd.

Panasonic Corporation

Panasonic Intellectual Property Management Co., Ltd.

Shigetaka Aoki

Katsuya Nozawa

Tohru Saitoh

Katsushige Yamashita

Akira Asai

Minoru Kubo

Teruhito Ohnishi

Kenichi Nishimura

Hidenori Notake

Atsuya Yamamoto

A semiconductor device includes: a silicon substrate that includes a high-concentration layer containing first conductivity type impurities; a low-concentration layer formed on the high-concentration layer and containing first conductivity type impurities; a first electrode and a second electrode formed on the low-concentration layer; a vertical semiconductor element that allows current to flow between the second electrode and the high-concentration layer; and a first trench unit that realizes electric connection between the first electrode and the high-concentration layer. The first trench unit consists of first polysilicon containing first conductivity type impurities, and a diffusion layer configured to surround the first polysilicon in a plan view and to contain first conductivity type impurities. The first polysilicon is configured to reach the high-concentration layer by penetrating the low-concentration layer. Respective concentrations of the first conductivity type impurities contained in the first polysilicon and in the diffusion layer are kept constant in a direction from the low-concentration layer to the high-concentration layer.

Semiconductor device

A semiconductor device includes a second conductivity type back gate electrode formed within a body area, and electrically connected with the body area, and performs bidirectional current control in a direction from a drain area to a source area and in a direction from the source area to the drain area. A sheet resistance of the back gate electrode is lower than a sheet resistance of the body area. The source area and the back gate electrode are disposed apart from each other with a clearance sufficient for preventing a breakdown phenomenon caused between the source area and the back gate electrode when a maximum operation voltage is applied between the source area and the drain area.

A SiGe-HBT having a base region made of SiGe mixed crystal. The base region includes: an intrinsic base region having junctions with a collector region and an emitter region; and an external base region for connecting the intrinsic base region with a base electrode. The intrinsic base region and the external base region are doped with a first impurity of a given conductivity type. The external base region is further doped with a second impurity. As the first impurity, an element smaller in atomic radius than Si (such as boron, for example) is selected, and as the second impurity, an element larger in atomic radius than the first impurity (such as Ge, In and Ga, for example) is selected.

Heterojunction bipolar transistor and fabrication method of the same

A base layer made of SiGe mixed crystal includes a spacer layer formed in contact with a collector layer with no base impurities diffused therein and an intrinsic base layer formed in contact with an emitter layer with base impurities diffused therein. The spacer layer contains C at a low concentration. The intrinsic base layer has a first region containing C at a low concentration on the collector side and a second region containing C at a high concentration on the emitter side.

Heterojunction bipolar transistor

Immediately after a Si/SiGe film containing a contaminant is formed over all surfaces of a substrate by epitaxial growth, a portion of the Si/SiGe film formed to the back surface side of the substrate is removed by wet etching. In addition, the Si/SiGe film is subjected to processing with heating in a container, after which a dummy run is carried out in the container. These processings prevent secondary wafer contamination through a stage, a robot arm or a vacuum wand for handling a wafer and the contamination of the container also used in the fabrication process of a semiconductor device free from any group IV element but Si.

Method for fabricating semiconductor device

A method of fabricating a semiconductor device according to the present invention includes a step A of forming a polycrystalline or amorphous preliminary semiconductor layer on a surface of a substrate so as to have an opening portion and a step B of simultaneously forming an epitaxial growth layer on an exposed portion of a surface of the substrate through the opening portion and a non-epitaxial growth layer on the preliminary semiconductor layer using a CVD method while heating the substrate inside a reaction chamber by means of a heat source inside the reaction chamber, the epitaxial growth layer being made of single crystalline semiconductor, and the non-epitaxial growth layer being comprised of a polycrystalline or amorphous semiconductor layer.

Method of forming a semiconductor device including simultaneously forming a single crystalline epitaxial layer and a polycrystalline or amorphous layer

An Si/SiGe layer including an Si buffer layer, an SiGe spacer layer, a graded SiGe layer and an Si cap layer is epitaxially grown in a region corresponding to a collector opening while a polycrystalline layer is deposited on the upper surface of a nitride film, and side surfaces of an oxide film and the nitride film. In this case, the Si buffer layer is formed first and then other layers such as the SiGe spacer layer are formed, thereby ensuring non-selective epitaxial growth. Then, a polycrystalline layer is deposited over the nitride film.

Semiconductor device and method for fabricating the same

A SiGe-HBT is provided with a SiGe film and a Si film grown in succession by epitaxial growth. The SiGe film is made up of a SiGe buffer layer, a SiGe graded composition layer, and a SiGe upper layer, in which the Ge content is substantially constant or changes not more than that of the SiGe graded composition layer. Even if there are fluctuations in the position of the EB junction, the EB junction is positioned in a portion of the SiGe upper layer, so fluctuations in the Ge content in the EB junction can be inhibited, and a stable high current amplification factor can be obtained. It is also possible to provide a SiGeC film instead of the SiGe film.

Growing community of inventors

Osaka, Japan

Shigetaka Aoki