Texas Instruments Corporation

Shigeshi Abiko

Frederic Boutaud

Gilbert Laurenti

Mark L Buser

Marc Couvrat

Yuji Ozawa

Eric Ponsot

Hiroshi Takahashi

Douglas E Deao

Jean-Pierre Giacalone

Eric L Badi

Herve Catan

Armelle Laine

Karim Djafarian

Vincent Gillet

Yves Masse

Alain Boyadjian

Gael Clave

Anne Lombardot

Jean-Marc Philippe Bachot

Francois Theodorou

Emmanuel Ego

Jack Rosenzweig

Walter A Jackson

Jean-Louis Tardieux

Laurent Ichard

Frederic Nidegger

David Russell

N M Ganesh

Shoji Saiki

Shintaro Mizushima

A processor ( ) is provided that is a programmable fixed point digital signal processor (DSP) with variable instruction length, offering both high code density and easy programming. Architecture and instruction set are optimized for low power consumption and high efficiency execution of DSP algorithms, such as for wireless telephones, as well as pure control tasks. The processor includes an instruction buffer unit ( ), a program flow control unit ( ), an address/data flow unit ( ), a data computation unit ( ), and multiple interconnecting busses. Dual multiply-accumulate blocks improve processing performance. A memory interface unit ( ) provides parallel access to data and instruction memories. The instruction buffer is operable to buffer single and compound instructions pending execution thereof. A decode mechanism is configured to decode instructions from the instruction buffer. The use of compound instructions enables effective use of the bandwidth available within the processor. A soft dual memory instruction can be compiled from separate first and second programmed memory instructions. Instructions can be conditionally executed or repeatedly executed. Bit field processing and various addressing modes, such as circular buffer addressing, further support execution of DSP algorithms. The processor includes a multistage execution pipeline with pipeline protection features. Various functional modules can be separately powered down to conserve power. The processor includes emulation and code debugging facilities with support for cache analysis.

Microprocessors

A processor ( ) is provided that is a programmable digital signal processor (DSP) with variable instruction length, offering both high code density and easy programming. Instructions may be executed during delay slots after program branching while an execution pipeline is being restarted. Architecture and instruction set are optimized for low power consumption and high efficiency execution of DSP algorithms, such as for wireless telephones, as well as pure control tasks. A software breakpoint instruction is provided for debugging purposes. In order to correctly emulate the operation of the instruction pipeline when a software breakpoint instruction is executed during a delay slot, the width ( ) of the software breakpoint is the same as the replaced instruction. A limited number of breakpoint instruction length formats ( ) are combined with non-operational instructions (NOP, NOP ) to form a large number of combination instructions that match any instruction length format.

Various length software breakpoint in a delay slot

An address generating circuit of simple configuration for repeating a selected block of instructions is provided. An instruction address maintained by program counter 72 is compared to register 76 that holds the address of the end of the selected block of instructions. When the end address is detected, the program counter is loaded with a starting address of the block of instructions, which is stored in register 80. Block repeat count register 86 maintains a repeat count. Zero detection circuit 70 delays decrements of register 86 by a number of clock cycles that is equivalent to a pipeline depth for instruction prefetching of a processor connected to program counter 72. The zero detection circuit 70 outputs a loop-end control signal which controls a selector to selectively provide an incremented address or the start address to the program counter. By delaying decrements of register 86, the state of the repeat count is correctly maintained when the processor pipeline is flushed during an interrupt. The zero detection circuit also deactivates the loop-end control signal for the number of clock cycles equivalent to the depth of the prefetch pipeline during the final repeat loop iteration(s) so that a loop with a block size less than or equal to the depth of the prefetch pipeline can be repeated the correct number of times.

Address generating circuit for block repeat addressing for a pipelined

Clock signal generating circuit for preventing occurrence of clock skew, totally preventing through current, and readily controlling the clock, which includes a master clock signal generating circuit 2M and a slave clock signal generating circuit 2S. The master clock signal generating circuit 2M generates a master clock signal MCLK at a high level based on a slave clock signal SCLK at a low level and a clock signal CLK at a low level, and generates a master clock signal MCLK at a low level based on the clock signal CLK at a high level. The slave clock signal generating circuit 2S generates a slave clock signal SCLK at a low level based on the clock signal CLK at a low level and a slave clock signal SCLK at a high level based on the master clock signal MCLK being at a low level and the clock signal CLK at a high level. A master clock delay generating circuit 3M inputs the slave clock signal SCLK as output from the slave clock signal generating circuit 2S to be able to set the delay time optionally in the master clock signal generating circuit 2M by delaying for the necessary time. Additionally, a slave clock delay generating circuit 3S is provided which inputs the master clock signal MCLK output from the master clock signal generating circuit 2M to be able to set the delay time optionally into the slave clock signal generating circuit 2S by delaying for the necessary time.

Clock signal generating circuit

An address generating circuit of simple configuration for circular addressing. A bit isolating circuit 304 extracts an index from an input address. When a step value input to an adder 302 is positive, an index generating circuit subtracts the sum of the index and step value from a block size of a memory region. Depending on the subtraction result, an output which is either the sum of the index and step value or the subtraction result is provided as a new index. When the step value is negative, the index and step value are added. Depending on the addition result, an output which is either the sum of the index, step value, and capacity of the memory region or the addition result is provided as a new index. A bit multiplexer 314 generates the next address from the new index and an address.

Address generating circuit for generating addresses separated by a

An arithmetic circuit is provided in which the circuit scale can be reduced and the circuit delay can be shortened. The upper 24 bits and lower 16 bits of the 40 bit data A and B, that is input into the arithmetic circuit 100, are calculated in the first arithmetic circuit 110 and the second arithmetic circuit 120, respectively. The carry transmission control circuit 130 transmits the carry between the arithmetic circuit 120 and the arithmetic circuit 110 when the arithmetic circuit dividing signal p does not divide the arithmetic circuit, and the command control circuit 140 outputs an identical command to each of the arithmetic circuits. As a result, this circuit becomes an arithmetic circuit of 40 bits. The carry transmission control circuit 130 stops the transmission of the carry between the arithmetic circuit 120 and the arithmetic circuit 110 when the signal p divides the arithmetic circuit, and the command control circuit 140 outputs each of the independent commands to each of the arithmetic circuits. As a result, this circuit becomes a parallel arithmetic circuit of 24 bits and 16 bits.

Arithmetic circuit

A transversal filter circuit including a plurality of tap circuits, each having a serial multiplication circuit having a simplified construction and not requiring a shift of decimal (binary) points of data during a partial product calculation and addition operation. The serial multiplier includes a bidirectional shift register for shifting a tap coefficient by a predetermined number of bits in one of two directions, a data input circuit, a partial product calculation circuit, an adding and holding circuit, and a control circuit. The control circuit alternatively changes the shift direction of the bidirectional shift register for shifting a tap coefficient and a data output direction of the data input circuit at each successive cycle. The partial product calculation circuit calculates a partial product of a tap coefficient from the shift register and the input data for a plurality of times defined by a bit number of the input data. The adding and holding circuit adds a newly calculated partial product to a sum of the partial products.

Transversal filter circuit having tap circuits including bidirectional

A method of and a circuit for generating address signals, wherein a binary index signal and a binary base address signal are stored in index and address registers, respectively, whereupon the index signal and the base address signal are added together to produce an initial output address signal representative of the arithmetic sum of the index and base address signals during an initial cycle of signal generating operation. The initial output address signal is tentatively storing in the address register and is added to the index signal to produce an output address signal differing in bit pattern from the initial output address signal during the cycle of signal generating operation immediately subsequent to the initial cycle. This output signal is likewise tentatively storing in the signal register and thereafter the index signal from the index register and the output address signal produced during each of the successive cycles of signal generating operation are added together to produce another output address signal differing in bit pattern from each of the output address signals produced during the immediately preceding cycle of signal generating operation, wherein the arithmetic sum is produced by carrying out a forward arithmetic addition from the least significant bits forward or a reverse arithmetic addition from the most significant bits backward.

Method of and circuit for generating bit-order modified binary signals

Growing community of inventors

Tokyo, Japan

Shigeshi Abiko