Kabushiki Kaisha Toshiba

Shigeru Yamada

Tetsuro Itakura

Tsutomu Takahashi

Isao Abe

Takuya Fujimoto

A source driver circuit device for decreasing a gap of output errors of a plurality of driver circuits which perform a serial/parallel conversion of a video signal, comprises a plurality of sample-and-hold circuits arranged in the order for sequentially sampling levels of an input video signal; a plurality of signal output circuits for respectively generating voltage outputs corresponding to holding levels of said plurality of sample-and-hold circuits; a plurality of reference level sample-and-hold circuits each of which is provided with each predetermined number of said sample-and-hold circuits, and for sampling a reference level; a plurality of sample value output circuits for respectively generating voltage outputs corresponding to holding levels of said plurality of reference level sample-and-hold circuits; and an output error correction circuit for performing an output level correction in each of said plurality of signal output circuits on the basis of a level difference between said reference level and an average value of a plurality of outputs issued from said plurality of sample value output circuits. Therefore, it is possible to decrease the level difference between output errors among the driver circuit device.

Source driver circuit device having improved level correction circuit

There is provided a potential data selection circuit suitable for use, e.g., in a device for driving a liquid crystal pane adapted for selecting an arbitrary one of a plurality of potential data to output the selected one. This potential data selection circuit comprises: a sample-hold circuit adapted for sampling and holding selection data of at least 2 bits to output them, and a decoder adapted to receive the selection data from the sample-hold circuit to decode them to output control signals. The potential data selection circuit further comprises a multiplexer including analog switches adapted to respectively receive at least two potential data, and responsive to the control signals from the decoder to control the operations of the analog switches to select any one of the potential data to output the selected one, and an output circuit adapted to receive the selected potential data to output a signal of a voltage of the selected potential data to the exterior.

Potential data selection circuit

A multiplexer circuit comprises a plurality of circuits for decoding digital timing signals, and a plurality of circuits for passing an one of the analogue voltage potentials to an output terminal corresponding to the decoded result of the decoding circuits, and preventing the passing circuits from passing more than one signal simultaneously.

Multiplexer circuit less liable to malfunction

A semiconductor memory device in which a data line and a holding circuit for storing data thereon are connected through a transmission gate comprised of an N-type MOS transistor and a P-type MOS transistor, wherein the semiconductor memory device comprises an initial potential setting circuit for setting an initial potiential on the data line prior to readout operation of data from the holding circuit; and a control circuit operative to allow the both transistors of the transmission gate to be turned on at the time of writing data into the holding circuit, and to allow one of the transistors to be turned on at the time of reading data from the holding circuit. Where a hold potential changes when data in the holding circuit has been read out onto the data line, such a change in the hold potential increases on resistance of one of the transistors which has been turned on of the transmission gate. As a result, this change in the hold potential in held down to a small value, so it does not reach the threshold voltage of the holding circuit.

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Yokohama, Japan

Shigeru Yamada