Sumco Corporation

Sumitomo Mitsubishi Silicon Corporation

Sumitomo Metal Industries, Inc.

Shigeru Umeno

Toshiaki Ono

Masataka Hourai

Eiichi Asayama

Koji Kato

Takashi Nakayama

Yasuo Koike

Hiroaki Taguchi

Yasuhiro Oura

Satoshi Murakami

Wataru Sugimura

Takeo Katoh

Shinsuke Sadamitsu

Tadami Tanaka

Hideshi Nishikawa

Masataka Horai

Kazuhisa Torigoe

Manabu Nishimoto

Kazumi Tanabe

Hirotaka Fujii

Keiichiro Hiraki

Shinichiro Miki

Kouji Sueoka

Wataru Itou

Masakazu Sano

Hisashi Katahama

Provided is a method of accurately predicting the thermal donor formation behavior in a silicon wafer, a method of evaluating a silicon wafer using the prediction method, and a method of producing a silicon wafer using the evaluation method. The method of predicting the formation behavior of thermal donors, includes: a first step of setting an initial oxygen concentration condition before performing heat treatment on the silicon wafer for reaction rate equations based on both a bond-dissociation model of oxygen clusters associated with the diffusion of interstitial oxygen and a bonding model of oxygen clusters associated with the diffusion of oxygen dimers; a second step of calculating the formation rate of oxygen clusters formed through the heat treatment using the reaction rate equations; and a third step of calculating the formation rate of thermal donors formed through the heat treatment based on the formation rate of the oxygen clusters.

Method of predicting thermal donor formation behavior in silicon wafer, method of evaluating silicon wafer, and method of producing silicon wafer

A silicon wafer having a BMD density of 5&#xd7;10/cmor more and 2.5&#xd7;10/cmor less in a region of 80 &#x3bc;m to 285 &#x3bc;m from the wafer surface when the silicon wafer is heat-treated at a temperature X (&#xb0; C., 700&#xb0; C.&#x2264;X&#x2264;1000&#xb0; C.) for a time Y (min) and then subjected to an infrared tomography method in which the laser power is set to 50 mW and the exposure time of a detector is set to 50 msec. The time Y and the temperature X satisfy Y=7.88&#xd7;10&#xd7;X.

Silicon wafer

This method for manufacturing a silicon wafer includes: a first heat treatment step of performing RTP treatment on the silicon wafer in an oxidizing atmosphere; a step of removing a region in the silicon wafer in which an oxygen concentration increases in the first heat treatment step; a second heat treatment step of performing, after performing this removing step, RTP treatment on the silicon wafer in a nitriding atmosphere or an Ar atmosphere; and a step of removing, after performing the second heat treatment step, a region in the silicon wafer in which an oxygen concentration decreases in the second heat treatment step. This method enables the manufacture of a silicon wafer in which latent defects such as OSF nuclei and oxygen precipitate nuclei existing in a Pregion are destroyed or reduced, and that has a gettering site.

Silicon wafer and method for manufacturing the same

An epitaxial silicon wafer cut from a silicon single crystal grown by the Czochralski method, and having a diameter of 300 mm or more. In this epitaxial silicon wafer, the time required to cool every part of the silicon single crystal during the growth from 800&#xb0; C. down to 600&#xb0; C. is set to 450 minutes or less, the interstitial oxygen concentration is from 1.5&#xd7;10to 2.2&#xd7;10atoms/cm(old ASTM standard), the entire surface of the cut silicon wafer is composed of a COP region, and the BMD density in the bulk of the epitaxial wafer after a heat treatment at 1000&#xb0; C. for 16 hours is 1&#xd7;10/cmor less. In this epitaxial silicon wafer, even if the thermal process in a semiconductor device fabrication process is a low temperature thermal process, epitaxial defects do not occur, as well as sufficient gettering capability being obtainable.

Epitaxial silicon wafer and method for manufacturing same

By determining a control direction of a pulling-up velocity without using a position or a width of an OSF region as an index, a subsequent pulling-up velocity profile is fed back and adjusted. A silicon single crystal ingot that does not include a COP and a dislocation cluster is grown by a CZ method, a silicon wafer is sliced from the silicon single crystal ingot, reactive ion etching is performed on the silicon wafer in an as-grown state, and a grown-in defect including silicon oxide is exposed as a protrusion on an etching surface. A growing condition in subsequent growing is fed back and adjusted on the basis of an exposed protrusion generation region. As a result, feedback with respect to a nearest batch can be performed without performing heat treatment to expose a defect.

Method of manufacturing silicon single crystal, silicon single crystal ingot, and silicon wafer

In this silicon single crystal wafer for IGBT, COP defects and dislocation clusters are eliminated from the entire region in the radial direction of the crystal, the interstitial oxygen concentration is 8.5&#xd7;10atoms/cmor less, and variation in resistivity within the wafer surface is 5% or less. This method for manufacturing a silicon single crystal wafer for IGBT includes introducing a hydrogen atom-containing substance into an atmospheric gas at a hydrogen gas equivalent partial pressure of 40 to 400 Pa, and growing a single crystal having an interstitial oxygen concentration of 8.5&#xd7;10atoms/cmor less at a silicon single crystal pulling speed enabling pulling of a silicon single crystal free of grown-in defects. The pulled silicon single crystal is irradiated with neutrons so as to dope with phosphorous; or an n-type dopant is added to the silicon melt; or phosphorous is added to the silicon melt so that the phosphorous concentration in the silicon single crystal is 2.9&#xd7;10to 2.9&#xd7;10atoms/cmand a p-type dopant having a segregation coefficient smaller than that of the phosphorous is added to the silicon melt so that the concentration in the silicon single crystals is 1&#xd7;10to 1&#xd7;10atoms/cmcorresponding to the segregation coefficient thereof.

Silicon single crystal wafer for IGBT and method for manufacturing silicon single crystal wafer for IGBT

A silicon wafer is produced through the steps of forming a silicon ingot by a CZ method with an interstitial oxygen concentration of not more than 7.0&#xd7;10atoms/cmand with a diameter of a COP occurring region not more than a diameter of a crystal, slicing a wafer from the silicon ingot after doping the silicon ingot with phosphorus, forming a polysilicon layer or a strained layer on one main surface of the wafer, and mirror polishing the other main surface of the wafer.

Silicon wafer and method for producing the same

It is possible to provide a silicon wafer that as well as being free of COPs and dislocation clusters, has defects (grown-in defects including silicon oxides), which are not overt in an as-grown state, such as OSF nuclei and oxygen precipitate nuclei existing in the PV region, to be vanished or reduced, by adopting a method for producing a silicon wafer, the method comprising the steps of: growing a single crystal silicon ingot by the Czochralski method; cutting a silicon wafer out of the ingot; subjecting the wafer to an RTP at 1,250&#xb0; C. or more for 10 seconds or more in an oxidizing atmosphere; and removing a grown-in defect region including silicon oxides in the vicinity of wafer surface layer after the RTP.

A single crystal silicon wafer for use in the production of insulated gate bipolar transistors is made of single crystal silicon grown by the Czochralski method and has a gate oxide with a film thickness of from 50 to 150 nm. The wafer has an interstitial oxygen concentration of at most 7.0&#xd7;10atoms/cm, a resistivity variation within the plane of the wafer of at most 5% and, letting t(cm) be the gate oxide film thickness and S (cm) be the electrode surface area when determining the TZDB pass ratio, a density d (cm) of crystal originated particles (COP) having a size at least twice the gate oxide film thickness which satisfies the formula d&#x2266;&#x2212;ln(0.9)/(S&#xb7;t/2). The wafers have an increased production yield and a small resistivity variation.

Single crystal silicon wafer for insulated gate bipolar transistors and process for producing the same

A silicon wafer for an IGBT is produced by forming an ingot having an interstitial oxygen concentration [Oi] of not more than 7.0&#xd7;10atoms/cmby the Czochralski method; doping phosphorus in the ingot by neutron beam irradiation to the ingot; slicing a wafer from the ingot; performing annealing of the wafer in an oxidizing atmosphere containing at least oxygen at a temperature satisfying a predetermined formula; and forming a polysilicon layer or a strained layer on one side of the wafer.

Silicon wafer for IGBT and method for producing same

Single crystal silicon wafer for insulated gate bipolar transistors

An active layer side silicon wafer is heat-treated in an oxidizing atmosphere to thereby form a buried oxide film therein. The active layer side silicon wafer is then bonded to a supporting side wafer with said buried oxide film interposed therebetween thus to fabricate an SOI wafer. Said oxidizing heat treatment is carried out under a condition satisfying the following formula:[]&#x2266;2.123&#xd7;10exp(&#x2212;(+273)),where, T is a temperature of the heat treatment, and [Oi] (atmos/cm) is an interstitial oxygen concentration.

Manufacturing method of silicon wafer

It is an object of the present invention to provide an epitaxial wafer with fewer pit defects in the epitaxial layer of a silicon monocrystalline wafer that has been doped with arsenic. Pit defects tend to occur when gas etching is performed prior to epitaxial film formation, but this tendency is reversed and a sound epitaxial layer is obtained by setting the crystal plane orientation to (100) and specifying the range of the tilt angle for the angle &#x3b8; in the [001] direction or [00] direction or the angle &#x3c6; in the [00] direction or [010] direction with respect to the [100] axis.

Epitaxial wafer and method for manufacturing method

A method for growing a silicon single crystal used for semiconductor integrated circuit devices, wherein the single crystal is grown by the CZ method at a nitrogen concentration of 1&#xd7;10atoms/cm&#x2013;1&#xd7;10atoms/cmwith a cooling rate of not less than 2.5&#xb0; C./min at a crystal temperature of 1150&#xb0; C.&#x2013;1000&#xb0; C., in which case, the pulling rate is adjusted such that the outside diameter of a circular region including oxidation-induced stacking faults generated at the center of a wafer which is subjected to the oxidation heat treatment at high temperature is not more than &#x2157; of the wafer diameter, wherein the wafer is prepared by slicing the grown single crystal. In the growth method, the concentration of oxygen in the silicon single crystal is preferably not more than 9&#xd7;10atoms/cm(ASTM '79). With this method, the silicon single crystal, in which the generation of Grown-in defects can be effectively suppressed, can be produced in a simple process without any increase in the production cost. Moreover, a specification of the oxygen concentration and the application of the outward diffusion treatment are capable of producing a wafer, which is optimally used for monitoring particles.

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Tokyo, Japan

Shigeru Umeno