Nippon Telegraph and Telephone Public Corporation

Takeda Riken Kogyo Kabushiki Kaisha

Takeda Riken Co., Ltd.

Shigeru Sugamori

Tsuneta Sudo

Yoshichika Ichimiya

Hiromi Maruyama

Susumu Sumida

Masao Shimizu

Kenji Kimura

Kohji Ishikawa

Naoaki Narumi

Takashi Tokuno

Toshiaki Wakita

An IC tester supplies test pattern signal to an IC being tested and compares response signals therefrom with an expected-value pattern signal to determine whether the IC is acceptable or not. During the test, the IC being tested is severed by a separator means from the drivers, for producing the test pattern signals with a timing signal generator set in a condition for generating reference signals. The reference signals and the outputs from the drivers are compared for phase by a phase comparator means. Variable delay means inserted in the paths of the test pattern signal are adjusted by the result of the comparison to suppress skews between the paths of the test pattern signals. Skews in strobe signals, which serve to determine the logic levels of the response signals output from the IC being tested, are also suppressed.

IC Tester

A memory device under test is accessed by an address generated by a pattern generator to write therein data and to read the data out to be compared with expected data, and the comparison result is stored in the fault-address memory by the same address after reading out therefrom the content of the address. When a disagreement is detected through the comparison, it is counted; however, the count operation is inhibited if the data read out from the fault-address memory is a fault data. When the counted number exceeds a predetermined value, a fault signal is generated. After the test is terminated, an address counter is operated, the fault-address memory is read out by the content of the address counter, and when fault data is detected from the output read out, the content of the address counter is fetched into the CPU.

Semiconductor memory device test apparatus

Input logical data is sequentially divided by a data dividing circuit for each time slot into n data trains, of which each data block has an n time slot length. A clock signal which can be arbitrarily timed, is divided by a clock dividing circuit into a n clock signals which are displaced one time slot apart in phase and which occur with a period of n time slots. In a logical circuit, the divided clock signals are controlled by the divided data trains corresponding thereto, and the controlled clock signals are time multiplexed by a multiplexing circuit, whereby output data with which the input logical data has been timed by the clock signal is obtained.

Logical waveform generator

Reference logical data is spatially divided by a data dividing circuit for each time slot, and the divided data are converted into data, each having a continuous effective period. The divided and converted reference data and input logical data are compared by comparators to detect whether or not they are coincident with each other. A clock signal for determining the timing of comparison is also divided by a clock signal dividing circuit into n clock signals which are displaced one time slot apart in phase and occurring with a period of n time slots. By these divided clock signals those of the outputs from the comparators corresponding thereto are taken out from a comparison output circuit.

High speed data logical comparison device

Growing community of inventors

Gyoda, Japan

Shigeru Sugamori