Adv Antest Corporation

Shigeru Sugamori

Rochit Rajsuman

James Alan Turnquist

Hiroaki Yamoto

Anthony Le

Yuya Watanabe

Robert F Sauer

Glen Gomes

Koji Takahashi

Bruce R Parnas

Rochit Rajusman

A test method for testing a device under test by using an event tester is provided. The test method includes: receiving a test signal generated by the event tester and applied to the device under test and sequentially writing the same to a memory; reading sequentially the written test signal from the memory at the speed higher than that of the test signal generated by the event tester and applying the same to the device under test; acquiring the output signal outputted from the device under test in response to the applied test signal and sequentially writing the same at the speed higher than that of the test signal generated by the event tester; sequentially reading the written output signal from the memory and transmitting the same at the speed lower than that of the output signal outputted from the device under test; and determining pass/fail of the transmitted output signal by the event tester.

Test method, test system and assist board

There is provided a test system that tests a device under test. The test system includes a test apparatus that tests the device under test on the basis of an event, and an added apparatus that is added between the device under test and the test apparatus when an interval to which a device output signal is changed is smaller than an interval capable of being processed by the test apparatus, and the added apparatus includes a signal input section that inputs the device output signal output from the device under test according to the device input signal, a change detecting section that detects whether the input device output signal has been changed or not, a change timing detecting section that detects the change timing for the device output signal, a storing section that sequentially stores the change timing and the signal value after the change for the device output signal as an output event, according to the fact that the device output signal has been changed, and a reading section that sequentially reads the output events from the storing section to input the events into the test apparatus.

Test system, added apparatus, and test method

An event based test system for testing an IC device under test (DUT) designed under an automatic electronic design (EDA) environment. The event based test system includes an event memory for storing event data derived directly from simulation of design data for an intended IC in the EDA environment where the event data to denote each event is formed with time index indicating a time length from a predetermined point and an event type indicating a type of change at an event, an event generation unit for generating test vectors based on the event data where waveform of each vector is determined by the event type and a timing of the waveform is determined by accumulating the time index of previous events, and means for supplying test vectors to the DUT and evaluating response outputs of the DUT at predetermined timings.

Event based IC test system

A semiconductor test system which generates a test pattern produced based on data resultant to device logic simulation performed on a computer for an LSI device designed in an electronic design automation (EDA) environment, tests the LSI device, and feedbacks the test results to the EDA environment. The semiconductor test system includes an event file for storing event data obtained by executing device logic simulation in a design stage of an LSI device under test; an event memory for storing the event data from the event file relative to timings; means for generating a test pattern by directly using the event data from the event memory and applying the test pattern to the LSI device under test; a result data file for evaluating a response output of the LSI device under test and storing resultant evaluation data; and means for evaluating design of the LSI device based on the data stored in the result data file.

Event based semiconductor test system

An apparatus and method in an event based test system for testing an electronics device under test (DUT). The apparatus includes an event memory for storing timing data and event type data of each event wherein the timing data of a current event is expressed by a delay time from an event immediately prior thereto with use of a specified number of data bits, and an additional delay time inserted in the timing data of a specified event in such a way to establish a total delay time of the current event which is longer than that can be expressed by the specified number of data bits in the event memory. The additional delay time is inserted by replicating the timing data and the event type data of the event immediately prior to the specified event.

Apparatus and method for successively generating an event to establish a total delay time that is greater than can be expressed by specified data bits in an event memory

An event based test system has a modular architecture for simultaneously testing a plurality of semiconductor devices (DUT) including memory and logic devices. The test system detects functional faults as well as physical faults in the DUT. The test system includes two or more tester modules each having a plurality of pin units, a main frame for accommodating the two or more tester modules, a test fixture for electrically connecting the tester modules and the DUT, a host computer for controlling an overall operation of the test system, and a data storage for storing a library of algorithmic test patterns and software tools for producing memory test patterns for testing memories. Memory test algorithm and information regarding the design and configuration of the memories to be tested are specified prior to the memory testing.

Modular architecture for memory testing on event based test system

A semiconductor test system for testing semiconductor devices has a plurality of different tester modules and an algorithmic pattern generator (ALPG) for generating an algorithmic pattern specific to an intended memory, thereby achieving a low cost and application specific memory test system. The semiconductor test system includes two or more tester modules whose performances are different from one another, an ALPG module for generating an algorithmic pattern which is specific to the memory, a test system main frame to accommodate a combination of the tester modules and the ALPG module, a test fixture for electrically connecting the tester modules and a device under test, a performance board provided on the test fixture for mounting the device under test, and a host computer for controlling an overall operation of the test system by communicating with the tester modules through a tester bus.

Application specific event based semiconductor memory test system

A semiconductor test system for testing semiconductor devices, and particularly, to a semiconductor test system having a plurality of different types of tester modules for easily establishing different semiconductor test systems. The semiconductor test system includes two or more tester modules whose performances are different from one another, a test head to accommodate the two or more tester modules having different performances, means provided on the test head for electrically connecting the tester modules and a device under test, and a host computer for controlling an overall operation of the test system by communicating with the tester modules through a tester bus. One type of the performances of the tester module is high speed high timing accuracy while other type of performance is low speed low timing accuracy. Each event tester module includes a tester board which is configured as an event based tester.

Module based flexible semiconductor test system

A semiconductor test system for testing a semiconductor device under test (DUT) is able to store failure data in a data failure memory with small memory capacity. The semiconductor test system includes a pattern memory for storing pattern data therein to produce a test pattern to be supplied to the DUT, means for evaluating an output signal of the DUT and producing failure data when there is a fail therein, a data failure memory for storing the failure data, and compaction means for assigning a plurality of addresses of the pattern memory to a single address of the data failure memory in a first test operation so that failure data occurred for each group of addresses of the pattern memory is stored in a corresponding address of the data failure memory, and for executing a second test operation for only a group of addresses of the pattern memory in which the failure data is detected without an address compaction.

Data failure memory compaction for semiconductor test system

An event based test system has a cost effective, error free, secure and simple way of managing the calibration data for all of the pin cards used therein. The test system has a large number of test channels for testing a semiconductor device under test (DUT) by applying test patterns to device pins of the DUT through the test channels and examining response outputs of the DUT. The test system includes a plurality of pin cards, each having a plurality of pin units therein to establish a part of the test channels, a non-volatile memory provided within each pin card for storing calibration data for compensating error factors involved in the pin units mounted in the corresponding pin card, and a microprocessor provided within each pin card for managing the calibration data and executing the calibration procedure for all of the pin units in the corresponding pin card, and wherein each pin unit is configured as an event tester in which a test, pattern or a strobe signal is directly generated based on event data stored in an event memory which define any changes from a previous event with reference to a time difference therefrom.

Event based test system storing pin calibration data in non-volatile memory

A power source current measurement unit provided in a semiconductor test system measures a power source current of a device under test with high speed and accuracy. The power source measurement unit includes a DA converter for generating a source voltage, an operational amplifier for supplying a power source current to the device under test, a voltage amplifier for amplifying a voltage representing the amount of power source current supplied to the device under test, an integration circuit for accumulating an output signal of the voltage amplifier for a predetermined integration time, and an AD converter for converting an output signal of the integration circuit to a digital signal after the integration time.

Power source current measurement unit for semiconductor test system

A semiconductor test system having a plurality of different types of tester modules for testing a mixed signal integrated circuit (IC) having analog signals and digital signals with high speed and high efficiency. The semiconductor test system includes two or more tester modules whose performances are different from one another, a test head to accommodate the two or more tester modules, means provided on the test head for electrically connecting the tester modules and a device under test, an optional circuit corresponding to the device under test when the device under test is a mixed signal IC, and a host computer for controlling an overall operation of the test system. Each event tester module includes a tester board which is configured as an event based tester.

Event tester architecture for mixed signal testing

An event based test system is configured to test an electronics device under test (DUT) by supplying a test signal to the DUT and evaluating an output of the DUT at a timing of a strobe signal. The event based test system includes an event memory for storing timing data of each event formed with an integer multiple of a reference clock period and a fraction of the reference clock period wherein the timing data represents a time difference between a current event and a reference point, an address sequencer for generating address data for accessing the event memory, a timing count and scaling logic for generating an event start signal, an event generation unit for generating each event based on the event start signal and data indicating the fraction of the reference clock period, and a host computer for controlling an overall operation of the event based test system.

A semiconductor test system having a power source current measurement unit for measuring a power source current of a device under test with high speed and accuracy. The power source measurement unit includes a DA converter for generating a source voltage, an operational amplifier for forming a negative feedback loop and supplying the source voltage to a power pin of the device under test thereby supplying a power source current to the power pin, a voltage amplifier for amplifying a voltage representing the amount of power source current supplied to the device under test, an integration circuit for integrating an output signal of the voltage amplifier for a predetermined integration time, and an AD converter for converting an output signal of the integration circuit to a digital signal after the integration time.

An event based test system for testing semiconductor devices under test (DUT). The event based test system is freely configured to a plurality of groups of sin units where each group is able to perform test operations independently from the other. The start and end timings of the test in each group are independently made by generating multiple end of test signals. The event based test system includes a plurality of pin units to be assigned to pins of the DUT, a signal generator for generating an end of test signal for indicating an end of current test which is generated for each pin unit independently from other pin units, and a system controller for controlling an overall operation in the event based test system by communicating with each pin unit. The end of test signal for each pin unit is selected by condition specified by the system controller and the selected end of test signal is provided to the system controller and to the other pin units.

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Santa Clara, CA, United States of America

Shigeru Sugamori