Fujitsu Corporation

Fujitsu Semiconductor Limited

Fujitsu Microelectronics Limited

Shigeru Nishio

Asao Kokubo

Hiroshi Daiku

Masatoshi Kokubun

Jun Funakoshi

Kohtaroh Gotoh

Naoaki Naka

Kazuhiro Terashima

Koji Aoyagi

A semiconductor integrated circuit including: a data input circuit inputting a data input signal from outside and outputting the signal; a comparison value register memorizing an expectation value of the output signal varying in accordance with an input to the data input circuit; and a comparing circuit comparing a value in accordance with a switching number of the output signal of the data input circuit and the expectation value, is provided.

Semiconductor integrated circuit

A semiconductor integrated circuit includes a check unit which compares a value of a pixel of interest with values of neighboring pixels contained in an image signal supplied from an image sensor, and determines based on the comparison whether the pixel of interest is defective, and a defect correcting unit which corrects the value of the pixel of interest by using values of surrounding pixels in response to the determination by the check unit that the pixel of interest is defective.

Circuit and method for correction of defect pixel

An image processing circuit for a color image sensor, comprising a color sensitivity correction circuit which adds/subtracts a predetermined offset to/from pixel signals being output by amplifying photoelectric conversion signals of pixels, which have photoelectric conversion element and are arranged in column and row directions, for each column, and multiplies the result by a predetermined gain, wherein the predetermined offset includes a first offset, which is set according to each color, and a second offset, which is set according to a plurality of columns. According to the present invention, the offset of the color sensitivity correction circuit includes a first offset, which is set according to each color, and a second offset, which is set according to a plurality of columns, therefore, periodic moir&#xe9; in the vertical direction, which is caused by the column output circuit and the output signal supply circuit for each column, can be suppressed, and image quality can be improved.

Image processing circuit providing improved image quality

A semiconductor integrated circuit includes a differential calculating unit which obtains a differential between a value of a pixel of interest and values of surrounding pixels contained in an image signal supplied from an image sensor, a dead-zone generating unit which defines a predetermined range of pixel values, and a comparison unit which checks whether the differential falls outside the predetermined range, wherein contour enhancement is applied to the pixel of interest in response to a determination by the comparison unit that the differential falls outside the predetermined range.

Circuit and method for contour enhancement

A test circuit is incorporated in a device having an output circuit for outputting a signal, and the test circuit carries out a verification of a connection of nodes of the device. The test circuit has a test data generating circuit and a test output buffer connected in parallel with output nodes of the output circuit. The test data generating circuit generates test data for carrying out a verification of a connection of the output nodes, and the test output buffer receives test data from the test data generating circuit and outputs the test data to the output nodes. Similarly, a test circuit is incorporated in a device having an input circuit for inputting a signal, and the test circuit carries out a verification of a connection of nodes of the device. The test circuit has a test data generating circuit and a test input buffer connected in parallel with input nodes of the input circuit. The test data generating circuit generates test data for carrying out a verification of a connection of the input nodes, and the test input buffer receives test data from the test data generating circuit and inputs the test data to the input nodes.

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Kawasaki, Japan

Shigeru Nishio