Fujitsu Corporation

Tokyo Shibaura Denki Kabushiki Kaisha

Tokyo Shibaura Electric Co., Ltd.

Shigeru Nagasawa

Masayuki Ikeda

Haruhiko Ueno

Naoki Shinjo

Kenichi Ishizaka

Kazushige Kobayakawa

Masami Dewa

Teruo Utsumi

Minoru Koshino

Tadao Amada

Keiichiro Uchida

Masanori Motegi

Moriyuki Takamura

Takatoshi Muraoka

Masayuki Katori

Naoki Sueyasu

Hiroshi Komatsuda

Ken-ichi Ishizaka

A parallel processing apparatus and method for processing data transferred between a plurality of processors each having a storage. Each of the plurality of processors corresponds a global virtual address in a global virtual memory space where a parallel processing between the plurality of processors is performed and a local virtual address in a local virtual memory space where an individual process in one of the processors is performed to an identical real address. Data is transferred from a first one of the plurality of processors to a second one of the plurality of processors by writing the data into the storage of the second processor according to the global virtual address or the local virtual address of the second processor, the second processor is notified of the global virtual address or the local virtual address of the transferred data, the notified global virtual address or the notified local virtual address is then translated into the real address which corresponds to the notified global virtual address or the notified local virtual address, data is read from the storage of the second processor to the second processor according to the translated real address, and the read data is calculated in the second processor.

Multiprocessor system and parallel processing method for processing data

In a parallel data processing control system for a parallel computer system having a plurality of computers and an adapter device connecting the computers to each other, a first unit, which is provided in the adapter device, transfers pieces of data processing progress state information to the computers. The pieces of the data processing progress state information respectively indicate data processing progress states of the computers. A second unit, which is provided in each of the computers, holds the pieces of the data processing progress state information. A third unit, which is provided in each of the computers, holds management information indicating a group of computers which share a data process. A fourth unit, which is provided in each of the computers, determines whether or not the computers in the group have completed the data process on the basis of the pieces of the data processing progress state information and the management information.

Barrier synchronizing mechanism for a parallel data processing control

A system information storage section stores access information showing attributes for accessing a storage peculiar to a processor and storages peculiar to other processors by relating the access information to data. The system information storage section stores space identifying information for identifying each of plural kinds of virtual spaces allocated according to applications of the storages. A plurality of address translation sections translate virtual addresses into real addresses, corresponding to the plural kinds of virtual spaces on the basis of the access information. A selection section selects any one of the plurality of address translation sections on the basis of the space identifying information. A transfer control section reads the data of the storage on the basis of the real address obtained by the selected address translation section and transfers the data to other processors together with the access information and the space identifying information.

Data transfer using local and global address translation and

A data processing unit is adapted to exchange data with another data processing unit via a network. The data processing unit includes a main storage for storing programs and data, an instruction processor for issuing transfer requests by executing programs stored in the main storage, and a transfer processor for enqueuing the transfer requests from the instruction processor into a transfer request queue, and for carrying out a transfer process between the main storage and the network based on each transfer request which is obtained from the transfer request queue. The transfer processor includes a failure display for displaying a failure when the failure occurs during the transfer process of each transfer request, a reference to and an erasure of a content of the failure display are possible from the instruction processor. The transfer process of the transfer request enqueued in the transfer request queue is prohibited during a time in which the failure is displayed in the failure display.

Transfer processor including a plurality of failure display units

Data processing unit

A synchronous processing system including a plurality of processors and a communications network. Each processor includes a synchronization combination storage element, status storage element, control element, judging element and shifting element. The synchronization combination storage element stores synchronization combination information showing a group of the processors being synchronized during the parallel execution of a program. The synchronous status storage element stores synchronous status information indicating that a synchronous waiting status is reached after the processor has finished its processing. A storage control element transmits the synchronous status information to all other processors. A judging element judges whether the group of processors are in synchronism based on the synchronization combination information and the transmitted status information. A processing shifting element shifts, when the group of processors are judged to be in synchronism, all the processors in the group to the next process of a program.

Synchronous processing method and apparatus for a plurality of

A transfer request queue control system for a parallel computer system includes a plurality of processing units each having a main storage storing instructions and data. An instruction processor reads the instructions from the main storage and executes the instructions. A transfer processor performs data transfers in packets, each comprising a header and body data and each data transfer comprising one or more packets. A network couples transmitting and receiving processing units, which are to perform a data transfer based on information included in the header of each packet, the header information being related to a destination of the data, an attribute of a memory access to the main storage and a length of the data. The transfer processor performs parallel processing by making a data transfer between the main storage and the network in successive packets, depending on the attribute of the memory access. The transfer processor of one of the processing units comprises a transfer request queue comprising a list of headers of respective packets corresponding to each of plural requested data transfers, a managing part for managing a transfer queue valid flag which indicates validity of a transfer request of the transfer request queue and a control part for performing a data transfer in response to a data transfer request and based on the transfer queue valid flag.

Transfer request queue control system using flags to indicate transfer

A parallel processing system including a plurality of processing units each having a main storage storing instructions and data, an instruction processor reading the instructions from the main storage and executing the instructions, and a transfer processor for making a data transfer in units of a packet which is made up of a header and body data. The parallel processing system further includes a network coupling two processing units which are to make the data transfer based on information included in the header of the packet, where the header includes information related to at least a destination of the data, an attribute of a memory access to the main storage and a length of the data. The transfer processor carries out a parallel process for each user process by making a data transfer between the main storage and the network in units of the packet depending on the attribute of the memory access. The transfer processor of at least an arbitrary one of the processing units includes a managing part for managing for each user process a transfer queue base address indicating a first address of a transfer queue in the main storage, a transfer queue write pointer indicating to which data transfer request of the transfer queue the instruction process has enqueued, a transfer queue read pointer indicating to which data transfer request of the transfer queue the transfer processor has finished the data transfer process, and a memory access virtual space.

Parallel processing system including instruction processor to execute

This invention relates to an abnormal packet processing system, and is directed to minimize processing of an abnormal packet during communication between a plurality of processing units by a receiving processor. This data processing system includes a plurality of processing units connected through an interconnection. At least one of the processing units is a transmitting processor which includes a unit for detecting an abnormality of a data packet during transmission of the data packet to a receiving processor; and a unit for adding abnormality report data to the data packet being transmitted and sending the data packet with the abnormality report data to the receiving processor, or, in the alternate, inhibiting transmission of the abnormal packet.

Abnormal packet processing system

Any two of multiple processor elements are coupled with each other via a data communication network that has a definite communication buffer length and includes multiple communication buffers. A packet having a header and body is created using processed data, and then transferred by a transmitting unit. After sending the processed data, the transmitting unit transmits dummy data, having a body which is longer than the communication buffer length in the data communication network, to the same receiving station as the one to which the processed data is transmitted. The transmitting unit then guarantees a processor element serving as a receiving station the arrival of preceding processed data and the header. Control data representing cache invalidation waiting is embedded in the header of the dummy data. When a transmitting end terminates transfer of the dummy data, the sending station can guarantee the termination of cache invalidation, which is performed by the processor element serving as a receiving station to attain the consistency of the contents of preceding storage data main storage and a cache memory.

Data communication system which guarantees at a transmission station the

In a multiprocessor system, transfer processing sections permit transfer of data and system information among a plurality of processors in order for the processors to perform parallel processing. The system includes physical processors within which virtual processors are realized and a plurality of logical processors corresponding to a plurality of processes to be processed. In transferring data and system information, each of the transfer processing sections selects a destination logical process number corresponding to a process to be transferred and reads from main storage physical processor and within-physical-processor virtual processor numbers corresponding to the logical processor number, data and system information for transfer toward a destination. In the destination, the physical or virtual processor executes the process.

Method and apparatus for processing and transferring data to processor

A multiprocessor system having a plurality of processors connected in parallel with each other through a network for performing mutual communication. Each processor includes a transfer queue unit for storing transfer requests, a main storage, a reception unit for receiving a transfer request from another processor, and a transmission unit for sending designated data to another processor when the transfer request is enqueued in the transfer queue unit. Each processor also includes a first register for storing information indicating whether the transfer queue unit is full, i.e. has an area available for storing a transfer request, and a second register for indicating whether a transfer request is a valid transfer request during a reception operation. A save unit is connected to the reception unit for temporarily saving a transfer request, and an enqueuing unit is provided for enqueuing a transfer request from the save unit to the transfer queue unit. An interruption processing unit receives an interrupt request from the reception unit, supervises the vacant/full state of the transfer queue unit, i.e. monitors whether the transfer queue unit has an area available for storing a transfer request, and outputs an enqueuing request to the enqueuing unit to realize the interrupt request.

Multiprocessor system including a transfer queue and an interrupt

A Darlington complementary circuit including first and second signal channel Darlington pairs each of which pair has an input and output transistor, wherein a diode is coupled in series with the base-emitter path of the output transistor of each pair to assure simultaneous turn-off of the transistors of each pair, and thereby prevent distortion of an output signal as one pair ceases operation and the other pair begins operation.

Darlington complementary circuit for preventing zero crossover distortion

A memory access control system in a vector processing system comprises a memory unit, a memory device, address holding registers, a shift register and data buffer registers. The memory access control system distinguishes each vector data read out from the memory unit based upon the address holding registers by the output of the shift register. The shift register stores vector element numbers indicated by the memory device and transfers same to the data buffer registers. Each number from 0 to n-1, of a vector A composed of n elements a.sub.0, a.sub.1, a.sub.2, . . . a.sub.n-1, is a vector element number and each data, from a.sub.0 to a.sub.n-1, is vector element data.

Memory access control system in vector processing system

A detector circuit comprising a detector element which includes a diode having a high-frequency input terminal which receives a predetermined DC bias voltage, and a parallel circuit constituted by a resistor and a capacitor and connected between the output terminal of the detector element and a ground terminal. The detector circuit is further provided with a resistor connected between the parallel circuit and the output terminal of the detector element.

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Kawasaki, Japan

Shigeru Nagasawa