Kabushiki Kaisha Toshiba

Tokyo Shibaura Denki Kabushiki Kaisha

Shigeru Morita

Takeo Maeda

Fumitomo Matsuoka

Hisao Yoshimura

Kikuo Yamabe

Naohiro Matsukawa

Hiroshi Nozawa

Masakazu Kakumu

A method for manufacturing a semiconductor device of the present invention has the step of forming an insulation material on a main surface of a semiconductor substrate. A groove is formed to extend from the surface of the material film to the substrate. The groove is buried with a first insulation film. By use of the first insulation film as an etching mask, the material film is removed, so that a projecting portion projecting to the first insulation film from the main surface can be obtained. A second insulation film is formed on a side surface of the projecting portion in a sloped shape, which is from the top portion of the projecting portion to the main surface.

Method for manufacturing semiconductor device isolation region

To planarize the surface of a semiconductor substrate having convex and concave portions as with the case of a trench structure or a multilayer interconnection structure, a burying film is formed all over the surface of the semiconductor substrate to bury the convex portions; a stopper layer is selectively formed on the burying film at the concave portions; and the burying film is removed flatwise by mechanical polishing until the surface of the convex portion is exposed. The method can simply realize a highly precise planarized structure. Further, it is also preferable to form another stopper layer on the surfaces of the convex portions.

Method of manufacturing semiconductor device

A method for manufacturing a semiconductor device of the present invention has the step of forming an insulation material on a main surface of a semiconductor substrate. A groove is formed to extend from the surface of the material film to the substrate. The groove is buried with a first insulation film. By use of the first insulation film as an etching mask, the material film is removed, so that a projecting portion projecting to the first insulation film from the main surface can be obtained. A second insulation film is formed on a side surface or the projecting portion in a slope shape, which is from the top portion of the projecting portion to the main surface.

Method for manufacturing semiconductor device

A semiconductor device has a nobel configuration. The device includes a semiconductor substrate, element isolation regions formed on the main surface of the semiconductor substrate and at least one element region formed on the main surface of the semiconductor substrate and enclosed by the element isolation regions. In the device, the depth of each trench from the main surface to the bottom of the semiconductor substrate is shallow at a region where the trench width is less than a specified length, and it is deep at a region where the trench width is larger than the specified length.

Semiconductor device having trench structure for element isolation

A dynamic type semiconductor memory device comprises a semiconductor substrate including a memory cell array, the memory cell array including two kinds of main memory cells and two kinds of dummy cells, a plurality of bit lines disposed above the semiconductor substrate and generally extending in a first direction, a plurality of word lines disposed above the semiconductor substrate and generally extending in a second direction so as to intersect the bit lines, and dummy word lines disposed above the semiconductor substrate and generally extending in the second direction so as to intersect the bit lines. In this case the main memory cells and the dummy cells are connected to the bit lines, the word lines and the dummy word lines, respectively, in such a manner that one of the main memory cells and one of the dummy cells each having the same kind are selected when any one of the main memory cells is selected. As one kind of the main memory cells, trench capacitor type memory cells are used, while stacked capacitor type memory cells are employed as the other kind of the main memory cells.

Dynamic type semiconductor memory device with dummy cells capable of

The present invention comprises a groove formed in a semiconductor substrate, a buried element isolation region formed in the groove, source and drain diffusion regions formed inside the buried element isolation region, an electrode wiring layer connected the buried element isolation region across the diffusion regions and constituted by a two-layered structure consisting of a control gate and a floating gate, and a side-wall diffusion region which extends along the groove, is in contact with the source and drain diffusion regions, and is formed at a position corresponding to at least the electrode wiring layer. As a result, the write characteristic of a non-volatile memory can be improved, and at the same time, the non-volatile memory can be micropatterned.

Semiconductor memory device having improved write characteristic

The present invention comprises a buried element isolation region, an inversion preventing impurity diffusion region formed in a groove of a semi-conductor substrate, a shallow channel impurity diffusion region, a deep channel impurity diffusion region, source and drain diffusion regions formed inside the buried element isolation region, an electrode wiring layer connected to the buried element isolation region across these diffusion regions, a first side-wall impurity diffusion region which is along the buried element isolation region, is in contact with the source and drain diffusion regions, and is formed at a position corresponding to at least the electrode wiring layer in a shallow region from the substrate surface, and a second side-wall impurity diffusion region formed in a deep region separated from the substrate surface at a position below the first side-wall impurity diffusion region and having an impurity concentration which is different from that of the deep channel impurity diffusion region and is also different from each of impurity concentrations of the inversion preventing impurity diffusion region and the first side-wall impurity diffusion region. For this reason, characteristics such as a threshold value, a punchthrough, and a back gate effect of the semi-conductor device can be freely controlled.

Mosfet with buried element isolation regions

This invention relates to a junction structure in which element isolation regions having different shapes (e.g., isolation regions respectively formed by a trench isolation method and a LOCOS method) for electrically isolating an element region formed on a semiconductor substrate are bonded to each other. A LOCOS isolation region made of an insulator for electrically isolating many circuit elements of an element region formed on a semiconductor substrate is formed. An end portion of the insulating trench isolation region bonded to the LOCOS isolation region is formed to have a sectorial shape. When a side serving as an end portion of the LOCOS isolation region is bonded to tapered sides of the sectorial portion of the trench isolation region to cause the tapered sides to cross and overlap each other, an included angle serving as an angle defined by these isolation regions on the element region is an obtuse angle.

Semiconductor device having junction structure of a plurality of element

In a method for manufacturing a semiconductor device using a LOCOS technique, a selective oxidation is performed using an oxidation-resistance film as a mask to form an element isolating oxide film on the semiconductor substrate. An inserting portion of the oxide film is formed under an end portion of the oxidation-resistance film. The feature of this method lies in that the inserting portion of the oxide film is left as an element isolating oxide film and the other portion thereof is removed to selectively expose the substrate, and then a monocrystalline silicon layer is formed on the exposed portion of the substrate and used as an element region.

Method of manufacturing a semiconductor device

A MOS structure is formed on a silicon semiconductor substrate surface using a first gate electrode film made of polysilicon, an element isolation groove reaching the inside of the silicon semiconductor substrate is formed, and an insulating film is filled in the groove. In addition, a second gate electrode film made of a refractory metal such as molybdenum silicide is formed to be connected to the first gate electrode film, and the first and second gate electrode films are simultaneously removed to form a MOS gate electrode and a wiring layer.

Semiconductor device having buried element isolation region

A method for manufacturing a semiconductor device with a lens section. A semiconductor element is formed in a semiconductor substrate and a transparent layer is formed on this semiconductor element. The transparent layer is patterned to form the lens section.

Method for manufacturing a semiconductor device having a lens section

A method for producing a semiconductor device comprises a step of forming a first gate insulation layer on a portion of a single crystal silicon substrate and forming a floating gate of polycrystalline silicon on the first gate insulation layer, a step of forming an oxide layer on the exposed portion of the substrate and on the floating gate, and a step of forming a control gate on the floating gate through the oxide layer. In the formation of the oxide layer, a nitride pattern layer is formed on the floating gate, the entire structure is oxidized by using the nitride pattern layer as a mask, thus forming a protective layer on the exposed portion of the substrate, the nitride pattern layer is removed, and the entire structure is again oxidized, thus forming a second gate insulation layer on the floating gate.

Method for producing a semiconductor device with a floating gate

A vapor growth method of forming deposition film on a plurality of substrates disposed within a cylindrical reaction vessel by causing flow of reaction gas under a reduced pressure through the reaction vessel, in which the treated surfaces of substrates are inclined to the upstream side of the reaction gas flow with respect to the axis of the reaction vessel and the individual substrates but the most upstream side one are each shifted in position with respect to the preceding one in a direction perpendicular to the axis of the reaction vessel.

Growing community of inventors

Fujisawa, Japan

Shigeru Morita