Mitsubishi Denki Kabushiki Kaisha

Mitsubishi Electric Engineering Company, Limited

Shigeru Mori

Hiroshi Miyamoto

Michihiro Yamada

Makoto Suwa

Masanori Hayashikoshi

Shigeru Kikuda

Tadato Yamagata

Mitsuya Kinoshita

Yoshikazu Morooka

Tomio Suzuki

Takeshi Kajimoto

Seiji Sawada

Tatsuya Fukuda

Hiroshi Akamatsu

Shinichi Jinbo

Tetsuya Aono

Kazutami Arimoto

Kiyohiro Furutani

Shuji Murakami

Hideshi Miyatake

Kenichi Yasuda

Takayuki Miyamoto

Shinji Kawai

Mikio Sakurai

Kei Hamade

Takuya Ariki

Motoko Hara

Kazuhiro Sakemi

Tooru Ichimura

In an SDRAM, when a spare column selection line is not used, access to a column selection line is started at a first time at which complementary column address signals are defined, and access to the column selection line is stopped until a second time at which the level of a redundant column decoder activation signal is defined when the spare column selection line is used. Compared with the case in which access to the column selection line is always stopped until the second time, the access speed is increased.

Semiconductor memory device with spare memory cell

An internal clock generating circuit 200 applies an external clock signal Ext.CLK to a clock buffer circuit 206 in response to activation of a chip select signal ext./CS. The clock buffer circuit 206 is synchronized with the external clock signal Ext.CLK to generate an internal clock signal int.CLK. In response to inactivation of an internal circuit activating signal .phi..sub.ACT for designating activating an operation of an internal circuit of an SDRAM, a clock input control circuit 204 stops transmitting the external clock signal Ext.CLK and an operation for generating the internal clock signal int.CLK is stopped.

Synchronous semiconductor memory device capable of reducing electricity

A detect circuit receives a write enable signal, a column address strobe signal and an output control signal to predetect a mode in which data is input from an input/output terminal. While a substrate potential generation circuit normally operates, a substrate potential holding circuit also operates when the detect circuit detects the mode in which data is input, so that biasing capability of a substrate potential generating portion is increased before the data is actually input from the input/output terminal.

Semiconductor device capable of preventing fluctuations of substrate

In a pipeline burst EDO operation, a latency circuit 215 detects change of an internal column address strobe signal ZCASF from an active state to a non-active sate in the first cycle, and brings a signal OEMB into an active state. When a writing operation mode is specified, and an internal output enable signal ZOEF is in an active state, an output buffer control signal OEM attains an active state in response to the first activation edge of the internal column address strobe signal ZCASF after activation of the signal OEMB. Since the signal OEMB has already been in an active state in the first cycle of the signal ZCASF, a delay time for change of the signal OEM in response to activation of the signal ZCASF in the second cycle can be decreased.

Synchronous type semiconductor memory device which can be adapted to

A pulse signal generating circuit includes a ring oscillator and an internal voltage generating circuit. The internal voltage generating circuit generates an internal voltage depending on an operation temperature. The internal voltage is low at a normal temperature, and is high at a high temperature. Each inverter in the ring oscillator is driven by the internal voltage supplied from the internal voltage generating circuit. Thereby, a period of a pulse signal increases at a normal temperature, and decreases at a high temperature.

Pulse generating circuit and a semiconductor memory device provided with

A semiconductor memory device is provided which can apply a voltage stress to every adjacent bit lines even when data is written using a data bit compression function in a burn-in test mode. More specifically, when data is written using the data bit compression function in the test mode, an input buffer circuit is brought to a state in which it receives a signal corresponding to a signal dq0 applied to a specific input/output terminal by a switch circuit controlled by a test mode specify signal TE in common. When an inversion designate signal INV is in an active state, a complementary signal corresponding to a signal obtained by inversion of signal dq0 by an inverting circuit is output to internal data buses IO0, ZIO0, and IO2, ZIO2. On the other hand, a complementary signal corresponding to signal dq0 is output to internal data buses IO1, ZIO1, and IO3, ZIO3.

Semiconductor memory device capable of operating with potentials of

A DRAM includes an output terminal, a memory cell array having a plurality of memory cells, a row decoder, a column decoder, an input/output circuit, a data extending circuit, an output buffer circuit, and a control circuit. The data extending circuit extends each data read out from the input/output circuit until a subsequent data is read out. The output buffer circuit responds to the extended data from the data extending circuit for providing output data sequentially to the output terminal. In response to an output control signal provided from the control circuit, the output terminal is set to a high impedance state before each output data is provided from the output buffer circuit.

Semiconductor memory device having extended data out function

An address generating circuit and an address switching circuit of a DRAM output address signals A0 to A11 according to a refresh cycle time set by the user being less than a predetermined value, and output address signals A0 to A10 according to the refresh cycle time being the predetermined value or more. A row decoder selects one word line in response to the signals A0 to A11, and selects two word lines in response to the signals A0 to A10. Since refresh is carried out by selecting two word lines when the refresh cycle time is at the predetermined value or more, disappearance of data can be prevented.

Semiconductor memory device

In a semiconductor memory device, a constant voltage is applied to a resistor having a positive temperature coefficient, whereby a first reference current flowing through that resistor is converted into a voltage by a resistor. That voltage is converted into a second reference current by a P channel MOS transistor, whereby a second current of a value equal to the value of the second reference current flows through each of a plurality of inverters by a current mirror circuit. These inverters are connected in a ring manner to form a ring oscillator. The first reference current becomes lower as the operating temperature rises, whereby the second reference current increases. As a result, the oscillator cycle of the ring oscillator becomes shorter as the operating temperature rises.

Oscillator circuit generating a clock signal having a temperature

An internal power supply circuit of the present invention includes a primary internal power supply potential supplying circuit, two auxiliary internal power supply potential supplying circuits, and a P channel MOS transistor. The internal power supply potential supplying circuit always supplies an internal power supply potential to a first output node based on an external power supply potential. One auxiliary internal power supply potential supplying circuit is activated in response to a control signal, and, when activated, supplies the internal power supply potential to the first output node. The other auxiliary internal power supply potential supplying circuit is activated in response to another control signal, and, when activated, supplies the internal power supply potential to a second output node. The P channel MOS transistor is connected between the first output node and the second output node. The P channel MOS transistor has a gate electrode receiving the control signal.

Power supply circuit for generating an internal power supply potential

A semiconductor memory device includes a plurality of memory blocks, i main row or column select lines extending over the plurality of memory blocks, and a decoder for selecting one of the main row or column select lines in accordance with an applied address signal. The decoder includes i outputs. Each of the memory blocks includes a plurality of memory cells arranged in rows and columns and at least (i+1) sub row or column select lines each for selecting one row or one column of memory cells. A shift redundancy circuit is provided for each of the memory blocks, for connecting the main row or column select line and the sub row or column select line. The shift redundancy circuit includes a switch circuit for connecting one main row or column select line to one of the plurality of adjacent sub row or column select lines, and a circuit for setting a connection path of the switch circuit. The shift redundancy circuit connects successively adjacent sub row or column select lines to main row or column select lines in one to one correspondence except a defective sub row or column select line associated with a defective bit.

Redundancy circuit for repairing defective bits in semiconductor memory

A semiconductor memory device includes a memory cell array (1) having a plurality of memory cells arranged in rows and columns, a plurality of column select lines (3) extending over the memory cell array and coupled to received column select signals generated by a column decoder (100), a plurality of power supply lines (4) provided in parallel with the column select lines to transfer a power supply voltage from a main power supply line (130), and a plurality of ground lines (5) provided in parallel with the column select lines to transfer a ground voltage from a main ground line. A plurality of fuse elements (6) are provided for each of the column select lines. When a short-circuit is found between a column select line and power supply line or a ground line, a fuse element corresponding to the short-circuited column select line is blown off and the short-circuited column select line is isolated from the column decoder. By repairing the short-circuited column select line with a redundant column select line (60), the memory device operates correctly without an adverse effect of the short-circuit.

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Hyogo, Japan

Shigeru Mori