Mitsubishi Denki Kabushiki Kaisha

Mitsubishi Electric Corporation

Agency of Industrial Science and Technology

Kozo Iizuka, Director General, Agency of Industrial Science and

Renesas Technology Corp.

Mitsubishi Electric Company

Mitsubishi Denki Kaisha

Kozo Iizuka, Director General, Agency of Industrial Science & Technology

Shigeru Kusunoki

Kazuyuki Sugahara

Tadashi Nishimura

Yasuo Inoue

Hideki Nakamura

Katsumi Nakamura

Katsuhiro Tsukamoto

Shigeki Komori

Masahide Inuishi

Norifumi Tokuda

Yasuo Yamaguchi

Hidekazu Oda

Takashi Kuroi

Tatsuhiko Ikeda

Kyusaku Nishioka

Shinichi Ishizawa

Takashi Ipposhi

Satoshi Shimizu

Yoshinori Okumura

Sho Tanaka

Shuichi Ueno

Akihiko Ohsaki

Koichi Mochizuki

Junji Yahiro

Yoshihiko Hirota

Takahiro Okuno

Minoru Kawakami

A semiconductor device includes a plurality of first transistor cells and a plurality of second transistor cells that are electrically connected in parallel between a collector electrode and an emitter electrode. A gate voltage on each of the plurality of first transistor cells is controlled by a first gate interconnection. A gate voltage on each of the plurality of second transistor cells is controlled by a second gate interconnection. A drive circuit is configured to: apply an ON-voltage of the semiconductor device to each of the first and second gate interconnections when the semiconductor device is turned on; and after a lapse of a predetermined time period since start of application of the ON-voltage, apply an OFF-voltage of the semiconductor device to the second gate interconnection and apply an ON-voltage to the first gate interconnection.

Driving method and drive circuit for semiconductor device

A semiconductor device has a semiconductor substrate, an insulating film, a semiconductor element and a resistance element. The semiconductor substrate has a first trench. The insulating film covers an inner surface of the first trench. The semiconductor element has an electrode. The resistance element is electrically connected to the electrode to form a resistance to a current flowing through the electrode, and is arranged in the first trench with the insulating film therebetween. Thereby, the semiconductor device can have a resistance element that has a small footprint and can pass a large current with high reliability.

Semiconductor device with a resistance element in a trench

A semiconductor device includes a semiconductor substrate including a semiconductor layer, a power device formed in the semiconductor substrate, a plurality of concentric guard rings formed in the semiconductor substrate and surrounding the power device, and voltage applying means for applying successively higher voltages respectively to the plurality of concentric guard rings, with the outermost concentric guard ring having the highest voltage applied thereto.

Semiconductor device

A semiconductor device includes a channel layer formed on a substrate, an insulating layer formed in contact with the channel layer, an impurity-doped first semiconductor layer formed on an opposite side of the insulating layer from the channel layer, an impurity-doped second semiconductor layer formed on an opposite side of the first semiconductor layer from the insulating layer, and a gate electrode formed on an opposite side of the second semiconductor layer from the first semiconductor layer. A quotient of an impurity density of the first semiconductor layer divided by a relative permittivity of the first semiconductor layer is greater than a quotient of an impurity density of the second semiconductor layer divided by a relative permittivity of the second semiconductor layer.

A semiconductor device includes: a rectifying element; an electrode pad electrically connected to the rectifying element; and a resistance and a depletion transistor arranged between the rectifying element and the electrode pad, and electrically connected to each other. The semiconductor device has a configuration in which the rectifying element, the resistance, the depletion transistor, and the electrode pad are serially connected. The semiconductor device is configured to generate a gate potential of the depletion transistor based on a difference in potential across the resistance and to produce a depletion layer in a channel of the depletion transistor based on the gate potential. As a result, a semiconductor device having reasonably large current at low voltage and small current at high voltage can be obtained.

A high voltage semiconductor device includes a semiconductor substrate, a p type base region in a first main surface, an ntype emitter region in the p type base region, an ntype cathode region adjacent to an end surface of the semiconductor substrate and not penetrating the semiconductor substrate, a ptype collector region in a second main surface, a first main electrode, a second main electrode, a third main electrode, and a connection portion connecting the second main electrode and the third main electrode. A resistance between the p type base region and the ntype cathode region is greater than a resistance between the p type base region and the ptype collector region. In the high voltage semiconductor device in which an IGBT and a free wheel diode are formed in a single semiconductor substrate, occurrence of a snap-back phenomenon is suppressed.

High voltage semiconductor device including a free wheel diode

A semiconductor device includes a substrate of a first conductivity type, a base region of a second conductivity type, a source region of the first conductivity type, a collector region of the second conductivity type, a trench gate, which is formed in a trench via a gate insulation film, an electrically conductive layer, which is formed within a contact trench that is formed through the source region, a source electrode, which is in contact with the electrically conductive layer and the source region, and a latch-up suppression region of the second conductivity type, which is formed within the base region, in contact with the electrically conductive layer, and higher in impurity concentration than the base region. The distance between the gate insulation film and the latch-up suppression region is not less than the maximum width of a depletion layer that is formed in the base layer by the trench gate.

A semiconductor device has a semiconductor substrate having a first main surface, a second main surface opposite to the first main surface, and a recess defined in the second main surface by side surfaces and a bottom surface, a semiconductor region provided in the bottom surface of the recess of the semiconductor substrate, semiconductor regions provided in the surface of a peripheral region on the second main surface side, and insulating films provided on the side surfaces of the recess to electrically insulate the semiconductor regions.

A semiconductor device in which a main current flows in a direction of the thickness of a semiconductor substrate, to attain desirable electric characteristics. P type semiconductor regions and N type semiconductor regions are alternately provided with an interval therebetween, both regions in a surface of a second main surface of a semiconductor substrate. Between the P type semiconductor regions and the N type semiconductor regions, trenches formed in the surface of the semiconductor substrate are filled with insulators, thereby forming trench isolation structures. Moreover, a second main electrode is formed in contact with both the P type semiconductor regions and the N type semiconductor regions.

Semiconductor device and manufacturing method thereof

A semiconductor device of the present invention is provided with a power device which has a semiconductor substrate having a first main surface and a second main surface that are opposed to each other and an insulating gate structure on the first main surface side, wherein a main current flows between the first main surface and the second main surface, that is to say, is provided with an insulating gate type MOS transistor structure wherein the thickness (t) of the semiconductor substrate is no less than 50 &#x3bc;m and no greater than 250 &#x3bc;m and a low ON voltage and a high withstanding capacity against breakdown are implemented in the first main surface. Thereby, a low ON voltage, the maintaining of the withstanding capacity against breakdown and the reduction of a switching loss on the high voltage side can be implemented.

Insulated gate transistor

Growing community of inventors

Tokyo, Japan

Shigeru Kusunoki