Renesas Technology Corp.

International Business Machines Corporation

Mitsubishi Denki Kabushiki Kaisha

Shigeru Kuriyama

Michio Komoda

Hiromi Fujita

Masanori Kurimoto

Hiroshi Minakata

Kazuya Shimizu

Chie Hiramine

Naoki Urano

Masahiko Oomura

Takeshi Shibagaki

The operating characteristic of a transistor, modeled by a resistive element having fixed resistance and a power source voltage that varies with time, is segmented into a linearity region in which a current increases as a gate potential varies and a saturation region in which the current gradually decreases as the gate potential remains at a constant level, so that gradual decrease in current in a saturation region of the transistor is properly reflected and a delay time is estimated in a precise manner.

Delay time estimation method and recording medium storing estimation program

The outputting of an output pulse produced in response to the inputting of a data pulse and a clock pulse to a D type flip-flop circuit is repeatedly simulated in a simulation process to extract a pulse time difference between the data pulse and the clock pulse as a timing verification checking value in a checking value extracting process on condition that the level of the output pulse becomes higher than a reference voltage until a simulation completion time and the pulse time difference is within a prescribed range. After the first simulation, an optimum simulation completion time, at which the levels of the data pulse, the clock pulse and the output pulse are respectively set to a constant high value, is determined to be place the optimum simulation completion time between a simulation start time and the simulation completion time, and the level of the output pulse is checked at the optimum simulation completion time in simulations following the first simulation. Therefore, a pulse time difference sufficiently made small can be rapidly and reliably extracted as a timing verification checking value.

Timing verification checking value extracting method

A gate delay calculation apparatus includes an R parameter storage file for prestoring a parameter for expressing a source resistance value of an RC model as a continuous time function, an R determination portion for selectively extracting the parameter prestored in the R parameter storage file from the amount of input waveform gradient and output load model and a gate delay determination portion for calculating gate delay based on the source resistance value expressed by the parameter extracted by R determination portion and the output load model.

Gate delay calculation apparatus and method thereof using parameter expressing RC model source resistance value

A method for generating a multisided patch in which the expression form of each boundary curve and topology of the curve network can freely be set, curve formulae can be simply input, and high continuity. By inputting data of boundary curves to multisided patch generator via editing means which generates and edits curves, and blending sweep surfaces in two stages, a free-form surface is generated as a surface interpolating them. That is, data of a plurality of boundary curves is inputted to multisided patch generator, each given curve is swept by sweeping means along the curves intersecting it to generate surfaces, and the surfaces are blended by blending means in two stages, thereby generating a free-form surface. Since the surface formulae can be defined on the basis of the curve formulae of the boundaries, topology of the curve network and the descriptive form of each curve can freely be set, so that the boundary curve formulae of a multisided patch can be simply input by directly drawing the curve shapes on defined two-dimensional planes. In addition, geometric continuity of the generated surface is high because continuity of the given curves is high.

Method and apparatus for generating a free-form surface

Growing community of inventors

Tokyo, Japan

Shigeru Kuriyama