Nec Corporation

Shigeru Kuhara

Hideo Toyoshima

Koichi Takeda

A PLL circuit detects a locked state as keeping always constant the ratio of an input signal to a locked state detection reference value by automatically and continuously changing the locked state detection reference value even when the frequency of the input signal is changed. A division ratio of a frequency divider in the PLL circuit is changed in response to an external signal. An analog signal Vc which is output from a loop filter 3 is applied to a delay circuit 7. When the analog signal Vc rises, a delay time Td of the delay circuit 7 decreases. The locked state detection reference value varies according to the frequency of the signal f1.

Phase-locked loop circuit having a lock state detecting function

A semiconductor memory which is capable of enhancing its memory utilization efficiency and suppressing an increase in the memory area is provided. The semiconductor memory is equipped with a plurality of main memory blocks and a single redundancy memory block. A test ROM having a test program stored therein is stored in a portion of the redundancy memory block. If a defective memory cell is present in one of the main memory blocks, control means replaces this main memory block with the redundancy memory block. The test ROM is moved to an area within the main memory block in which the defective memory cell is not present.

Memory block replacement system and replacement method for a

First and second inverting stages and first and second decoding stages form in combination a decoder circuit, each of NAND gates of the first and second decoding stages and each of inverters of the first and second inverting stages are implemented by bi-MOS circuits, respectively, and the bi-MOS circuit for the NAND gate and the bi-MOS circuit for the inverter are a high-speed large-current consumption type and a low-speed small-current consumption type so that the decoder circuit achieves a high switching speed without sacrifice of power consumption.

High speed bi-MOS logic circuit operative under low power voltage

A semiconductor memory system is provided in which a wave-pipeline operational frequency is enhanced by reducing the cycle time through a reduction in a difference in the signal delay time caused by differences of data path lengths. A delay circuit is inserted into a signal path having a smaller delay time between an address input section and data output section, thereby reducing a difference in the signal delay time caused by differences of data path lengths, which in turn reduces the cycle time to enhance the wave-pipeline operational frequency. Alternatively, an arrangement may be made to increase the signal delay time of a driver and/or sense amplifier for a smaller signal path length. In another aspect, a maximum differences in voltage drops between memory cells is reduced by controlling the resistance of a charge section for a bit line.

High-speed semiconductor memory system

A semiconductor memory includes a plurality of first memory cell arrays, a pair of first common data lines which are provided for the plurality of first memory cell arrays, and a sensing section including a pair of first bipolar transistors whose emitters are respectively connected to the first common data lines and first constant current sources. Each first memory cell arrays includes a plurality of second memory cell arrays, a pair of second common data lines, a first differential amplifier including a second constant current source and a pair of second bipolar transistors whose bases are respectively connected to the second common data lines, whose bases are connected to the second constant current source together, and whose collectors are connected to the first common data lines, and a third constant current source of a second differential amplifier. Each second memory cell arrays includes a plurality of third memory cell arrays, a pair of third common data lines, a pair of third bipolar transistors whose bases are respectively connected to the third common data lines, whose emitters are connected to the third constant current source together to constitute the second differential amplifier, and whose collectors are respectively connected to the second common data lines, and a first control circuit for selectively activating the pair of third bipolar transistors. Each third memory cell arrays includes a pair of bit lines, a plurality of memory cells connected to the pair of bit lines, and a second control circuit for selectively connecting the pair of bit lines to the pair of second common data lines.

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Tokyo, Japan

Shigeru Kuhara