Sharp Kabushiki Kaisha Corporation

Shigeru Kitano

Daisuke Mochizuki

Soichi Onishi

Kinya Morinouchi

A card reader control system includes a measuring device which measures a time interval of a clock signal which is developed from a card reader when a card is manually driven to travel in the card reader. The card reader control system stores the maximum time interval and the minimum time interval of the clock signal measured by the measuring device. When either one or both of the maximum time interval and the minimum time interval is not included in a preferred range, an alarm buzzer is enabled to indicate that the card speed is not suited for the reading operation.

Card speed determination in a card reader

A CRT display control system controls a character display operation on a CRT image screen. The entire character line height is divided into a display allowed raster section and a display inhibited raster section. The display allowed raster section is provided for displaying characters. The display inhibited raster section functions as a line spacing. When the character matrix size is changed, the display allowed raster section and the display inhibited raster section are modified through the use of a preset system so that the line spacing is easily determined without modifying the circuit construction.

CRT display control system

A data reader reads data from a magnetic tape using a reproduction head. This data is presented to a loading control circuit which amplifies the signal produced by the reproduction head, as needed. The sufficiency of the volume level produced by the loading control circuit is detected by a volume adjustment detection circuit which detects the sufficiency of the signal level. If the signal level is insufficient, a buzzer is sounded indicating to the operator of the data reader that the gain level of the loading control circuit is insufficient. If the gain level is determined to be sufficient by the volume adjustment detection circuit, a signal path to a data detection circuit is enabled. The data detection circuit determines the presence of actual data and presents this data to a readout circuit.

Data processor for recording and reading out check data and true data in

An improved modulator is capable of facilitating recording and reproducing on and from an audio cassette tape digital signals such as programs and numerical data coming from digital signal processing apparatus including an electronic cash register as well as providing safety for the audio cassette tape when in operation. The modulator includes a control circuit for detecting and counting carrier signals and outputting desired information in response to a data transfer instruction and a state detector governed by the control circuit wherein the carrier signals are sent out via data transfer lines when the detector is in a specific state. The control circuit may be implemented with a microprocessor.

Modulator for use in an interface between a digital signal processing

A data recorder for recording data in the form of audio or digital signals into a cassette tape comprises a first circuit for recording check signals and a second circuit for recording true signals. The first circuit allows the check signals to be recorded in a first section of the cassette tape to check the amplitude of a sound volume in which the check signals are sounded. The second circuit enables the true signals to be recorded in a second section of the cassette tape under the condition that the amplitude of the sound volume of the check signals is adequately adjusted. A data reader for reading out the thus recorded data includes a first detection circuit for determining whether the read-out signals have a sufficient level for reading out purposes, an announcing device for announcing the need to adjust a sound volume, and a read-out circuit for reading out true data from the cassette tape.

An electronic apparatus comprises a central processor unit (CPU) for controlling the operation of the electronic apparatus, and a dynamic random access memory (RAM). The CPU develops a refresh control signal for refreshing the memory data stored in the dynamic RAM. An additional refresh control circuit is provided outside of the CPU for developing another refresh control signal. The additional refresh control circuit is connected to receive the electric power from a backup battery included in the electronic apparatus. When the service interruption occurs, the additional refresh control circuit is enabled to maintain the memory data stored in the dynamic RAM.

Growing community of inventors

Nara, Japan

Shigeru Kitano