Mitsubishi Denki Kabushiki Kaisha

Renesas Technology Corp.

Mitsubishi Electric Engineering Company, Limited

Shigeru Kikuda

Hiroshi Miyamoto

Shigeru Mori

Yoshikazu Morooka

Makoto Suwa

Mitsuya Kinoshita

Kiyohiro Furutani

Michihiro Yamada

Takeshi Hamamoto

Takashi Kono

Mikio Asakura

Yasuhiko Tsukikawa

Tetsushi Tanizaki

Shigehiro Kuge

Satoshi Kawasaki

Shinji Kawai

Kazuhiro Sakemi

Katsuya Furue

A plurality of semiconductor integrated circuits and a plurality of TEG circuits are aligned and provided on a substrate. In the TEG circuit, a built-in test circuit is provided in a region which faces a semiconductor integrated circuit across a dicing line region. The built-in test circuit and the semiconductor integrated circuit are connected by an interconnection which is provided on the dicing line region. The interconnection is cut for isolation into chips.

Semiconductor device capable of shortening test time and suppressing increase in chip area, and method of manufacturing semiconductor integrated circuit device

In a set of memory cells selected by one column select line, a memory cell of at least 1 bit is connected to an internal data line that is different from the internal data line to which another memory cell in the same set is connected. An internal data line pair is connected to a data terminal. Thus, data having different logic levels can be written into adjacent memory cells even in an IO compression test mode.

Semiconductor memory device with IO compression test mode

A dummy pattern that is inserted to stabilize the form of a transistor active region is implanted with an impurity of the same conductivity type as a well, and the impurity-doped region of the dummy pattern is supplied with a potential through a metal interconnection. Hence, fluctuation of a well potential due to noise hardly occurs, and a semiconductor device enduring latch up, for example, to a greater extent can be provided.

Semiconductor device with improved noise resistivity

I/O lines in an I/O gate-sense amplifier portion are arranged in the order of IOA, /IOB, IOB, and /IOA. As a result, the potentials of adjacent I/O lines are necessarily different at the time of writing/reading the same data to/from a plurality of memory cells during a multi-bit test. Therefore, a short-circuit fault caused between adjacent I/O lines can be detected at the same time.

Semiconductor memory device with improved test efficiency

Disclosed is a semiconductor memory device including a normal memory array and preliminary memory array enabling a mutual data transfer. Word lines in the normal memory array and those in the preliminary memory array are controlled by separate row decoders and separate word drivers. Bit lines and sense amplifiers are provided commonly to the normal memory array and the preliminary memory array. When test data is written in a predetermined pattern into the normal memory array, data corresponding to the predetermined pattern is written in advance for each memory cell in the preliminary memory array. Then, after the row decoder and word driver for the preliminary memory array are enabled so that the word lines in the preliminary memory array are activated, the row decoder and word driver for the normal memory array are enabled so that the word lines in the preliminary memory array are activated. Thus, data signals read from memory cells of one row in the normal memory array are simultaneously amplified by the sense amplifiers via the bit lines and then transferred via the bit lines to memory cells of one row in the preliminary memory array. In this result, the test data are written at one time into the memory cells of one row in the normal memory array.

Semiconductor memory device having fast data writing mode and method of

In a memory cell array, data lines are formed into a hierarchical arrangement of sub data lines provided for every block and a main data line common to each block, and a sub data line selected by a column address among sub data lines belonging a block which are simultaneously selected by a row address is connected to a bit line. Accordingly, the sub data line length is reduced, which reduces floating capacitance, reading and writing operations can be conducted at a high speed, and sub data lines can be selectively operated. In addition, power required for charging the sub data lines can be reduced, and entire power consumption by the semiconductor memory device can be reduced as well.

Semiconductor memory device permitting high speed data transfer and high

A semiconductor memory device includes a plurality of memory blocks, i main row or column select lines extending over the plurality of memory blocks, and a decoder for selecting one of the main row or column select lines in accordance with an applied address signal. The decoder includes i outputs. Each of the memory blocks includes a plurality of memory cells arranged in rows and columns and at least (i+1) sub row or column select lines each for selecting one row or one column of memory cells. A shift redundancy circuit is provided for each of the memory blocks, for connecting the main row or column select line and the sub row or column select line. The shift redundancy circuit includes a switch circuit for connecting one main row or column select line to one of the plurality of adjacent sub row or column select lines, and a circuit for setting a connection path of the switch circuit. The shift redundancy circuit connects successively adjacent sub row or column select lines to main row or column select lines in one to one correspondence except a defective sub row or column select line associated with a defective bit.

Redundancy circuit for repairing defective bits in semiconductor memory

A semiconductor device according to the present invention includes on the main surface of a p substrate a storing circuit region and peripheral circuit regions. An n well surrounds a p well including the storing circuit region and a p well including the peripheral circuit regions. As a result, a capacitance element is formed in the semiconductor substrate. It is possible to miniaturize the semiconductor device, and to improve reliability of connection between elements.

Semiconductor device and manufacturing method thereof

A chip is divided into at least four regions of two rows and two columns. In each region, memory array blocks are provided between corresponding first control circuits disposed in the column direction at a constant pitch. A column decoder is disposed adjacent to the first control circuit. Second control circuits are disposed corresponding to the first control circuits. The second control circuits excluding the second control circuit on the column decoder side are formed in the same pattern.

Semiconductor memory device suitable for high integration

A semiconductor memory device includes a memory array. The bit line pairs of the odd number order in the memory array belong to a first group, and the bit line pairs of the even number order belong to a second group. A first amplifier is connected to each bit line pair. Corresponding to the first group, write buses read buses and a read/test circuit are provided. Corresponding to the second group, write buses read buses and a read/test circuit are provided. A column decoder selects a plurality of bit line pairs simultaneously at the time of testing. At the time of testing, each of the read/test circuits compares data read out from the plurality of bit line pairs belonging to the corresponding group with a given expected data for providing the comparison result.

Semiconductor memory device comprising a test circuit and a method of

A plurality of sub chips are formed on a chip. An input/output buffer region is arranged around the plurality of sub chips. Each sub chip includes a sub chip control circuit region and a plurality of memory cell array blocks. Each memory cell array block includes a memory cell array region, a row decoder and control circuit region, a sense amplifier region and an input/output latch region.

Semiconductor integrated circuit device including a plurality of cell

Column repairing circuits 7a, 7b for repairing a DRAM in which there are defective memory cells in two columns are disclosed. The connection state of switching elements or circuits 51-5n, 61-6n, 71-7 (n+1), 81-8 (n+1) is determined as illustrated by appropriately disconnecting fuses in fuse links provided respectively in circuits 7a, 7b. Accordingly, column selecting lines Y2a and Y (n+1) b in memory array blocks 891a, 891b are not activated. The two repairing circuits 7a, 7b are provided spaced apart from each other on a semiconductor substrate, so that excessive concentration of fuse elements and switching elements or circuits is prevented.

Semiconductor memory device having multiple memory arrays and including

A semiconductor device having amplifying circuits provided near corresponding bonding pads receiving external signals, and positioned between the bonding pads and internal circuits to which such external signals are to be applied. The device includes a control signal generating circuit for the amplifying circuits which is not provided in conventional semiconductor devices. In response to external control signals, the control signal generating circuit generates internal control signals for controlling electric paths between a power supply and ground in the amplifying circuits. During the standby period of the semiconductor device, the paths between the power supply and ground are cut regardless of the potential of the corresponding bonding pads, preventing flow of a through current.

Semiconductor device having no through current flow in standby period

The semiconductor circuit device includes a first column decoder for decoding an internal column address and generating a column select signal which selects one column, and a second column decoder for simultaneously selecting a plurality of successively adjacent columns from a memory cell array in accordance with the column select signal. The second column decoder selects the same column in a duplicated way in response to different column select signals. Since the same column is selected in a duplicate way by the different column select signals, it will be possible to simultaneously select a desired combination of a plurality of columns. A combination of a plurality of columns simultaneously selected can be arbitrarily set and a desired combination of columns can be selected with a simplified circuit structure at high speed. It will be possible to repair a column containing a defective bit without providing a redundant column by providing an input/output control circuit for further selecting a column from the columns simultaneously selected in accordance with the column select signal.

Semiconductor circuit device having multiplex selection functions

A semicondcutor memory device includes an array of a plurality of memory cells arranged in a matrix manner, and a row or column decoder responsive to an external address signal for generating a row or column selecting signal. The memory cell array comprises (n+1) rows or columns. The row or column decoder comprises n output nodes. Transmission gates are provided between the decoder output node and row lines or column selecting lines for connecting each output node and each row line or column selecting line. The transmission gates are formed of a pair of CMOS transmission gates, whereby one output node is connected to two adjacent row lines or column selecting lines. This memory device further includes a circuit defining the connection manner of the transmission gate. This defining circuit turns one pair of CMOS transmission gates ON and OFF complementally. When there is a defective memory cell, the decoder output nodes are grouped into a first group including the output node corresponding to the faulty row or column having the defective memory cell, and a second group formed of the remaining output nodes. The defining circuit applies control signals to the CMOS transmission gates so that the ON/OFF states of the CMOS transmission gate pair related to the first group of output nodes and the CMOS transmission gate pair related to the second group of output node differ. The memory device further includes switching devices provided corresponding to each row line or column selecting line, responsive to the control signal from the defining cirucit to be turned on/off. This switching device connects only the faulty row line or the faulty column selecting line to the reference potential fixedly.

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Hyogo, Japan

Shigeru Kikuda