Sony Corporation

Sony Semiconductor Solutions Corporation

Sony Group Corporation

Shigeru Kanematsu

Hirokazu Ejiri

Hiroyuki Miwa

Takayuki Gomi

Masashi Yanagita

Takashi Noguchi

Hideki Mori

Katsuyuki Kato

Yuki Yanagisawa

Hiroaki Anmo

Norikazu Ouchi

Kenichi Ookubo

Matsuo Iwasaki

Hiroaki Ammo

Katsuhiko Takeuchi

Satoshi Taniguchi

Shinichi Wada

Takanori Higashi

[Overview] [Problem to be Solved] To provide a switching transistor and a semiconductor module having lower distortion generated in a signal. [Solution] A switching transistor including: a channel layer including a compound semiconductor and having sheet electron density equal to or higher than 1.7&#xd7;10cm; a barrier layer formed on the channel layer by using a compound semiconductor that is of a different type from the channel layer; a gate electrode provided on the barrier layer; and a source electrode and a drain electrode provided on the barrier layer with the gate electrode interposed between the source electrode and the drain electrode.

Switching transistor and semiconductor module to suppress signal distortion

A transistor including a carrier transit layer that includes a compound semiconductor and a carrier supply layer in contact with the carrier transit layer. The carrier supply layer includes a compound semiconductor of a different type from the carrier transit layer. The transistor includes a gate electrode provided on the carrier supply layer, and a source electrode and a drain electrode provided on another surface of the carrier transit layer that is opposite to one surface on which the carrier supply layer is provided.

Transistor, semiconductor device, electronic apparatus, and method for producing transistor

A semiconductor unit with memory devices, each of the memory devices includes: a first semiconductor layer; second and third semiconductor layers; a first dielectric film and a first conductive film; first, second, and third electrodes electrically connected to the second semiconductor layer, the third semiconductor layer, and the first conductive film, respectively, the third electrode being electrically connected to the first electrode. In the memory devices, when a voltage equal to or higher than a predetermined threshold value is applied between the first and second electrodes, a filament that is a conductive path electrically linking the second and third semiconductor layers is formed in the region between the second and third semiconductor layers, and thereby, writing operation of information is performed.

Memory device, semiconductor unit and method of operating the same, and electronic apparatus

A diode includes a first semiconductor layer configured by a compound semiconductor containing impurities of a first conductivity type; a high dislocation density region; a second semiconductor layer which is laminated on the first semiconductor layer, which is lower in a concentration of impurities in a region of a side of an interface with the first semiconductor layer than that of the first semiconductor layer, and which has an opening in which a portion which corresponds to the high dislocation density region is removed; an insulating film pattern which is provided to cover an inner wall of the opening; an electrode which is provided so as to cover the insulating film pattern and to contact the second semiconductor layer; and an opposing electrode which is provided to interpose the first semiconductor layer, the second semiconductor layer and the insulating film pattern between the electrode and the opposing electrode.

Diode and method of manufacturing diode

A semiconductor device includes: a device region having a semiconductor layer that includes a channel section; a device peripheral region adjoining the device region; a gate electrode provided within the device region, and having a boundary section that spans the device region and the device peripheral region; a conductive layer provided between the gate electrode and the semiconductor layer; and an insulating layer provided between the gate electrode in the boundary section and the semiconductor layer.

Semiconductor device and electronic apparatus

An operation method of a semiconductor device, includes providing one or more memory elements each including a first semiconductor layer, second and third semiconductor layers, a dielectric film and a conductive film, a first electrode, a second electrode, and a third electrode, and performing operation of writing information on a memory element to be driven of the one or more memory elements. The operation of writing is performed by forming a filament in a region between the second and third semiconductor layers, which is a conductive path electrically linking these semiconductor layers, the filament being formed by causing a dielectric breakdown of at least a part of the dielectric film, through application of a voltage equal to or higher than a predetermined threshold between the second and third electrodes, thereby causing an electric current to flow between the conductive film and the third semiconductor layer.

Semiconductor device and operation method thereof

An operation method of a semiconductor device, includes providing one or more memory elements each including a first semiconductor layer of a first conductivity type, second and third semiconductor layers of a second conductivity type, which are disposed to be separated from each other in the first semiconductor layer, a first electrode electrically connected to the second semiconductor layer, and a second electrode electrically connected to the third semiconductor layer, and performing operation of writing information on a memory element to be driven of the one or more memory elements. The operation of writing is performed by forming a filament in a region between the second and third semiconductor layers, which is a conductive path electrically linking these semiconductor layers, through application of a voltage equal to or higher than a predetermined threshold between the first electrode and the second electrode.

The present invention is related to a semiconductor device that forms an inductor on the same semiconductor substrate together with other active elements and a manufacturing method thereof. The semiconductor device of the present invention comprises a first conductivity type substrate, first semiconductor layer of a first conducting type with an impurity concentration lower than the substrate and a second semiconductor layer of a second conducting type on the first layer, an insulating film formed on this high-resistance semiconductor layer, and an inductor formed on this insulating film. The inductor has conducting film defining a width of the inductor. The first and second semiconductor layers are each formed under and at least as long as the width of the inductor.

Semiconductor device and manufacturing method thereof

Disclosed is a semiconductor device in which the capacitive element of MIMC structure has a low parasitic capacity. A process for fabrication of said semiconductor device. The semiconductor device has a capacitive element of MIMC structure, a PN photodiode, and a vertical NPN bipolar transistor which are mounted together on the same semiconductor substrate. The lower wiring layer connected to the TiN lower electrode layer of the capacitive element of MIMC structure is formed on the insulating film and the first interlayer insulating film. Between this insulating film and the p-type semiconductor substrate is the p-type low-concentration semiconductor layer whose impurity concentration is lower than that of the p-type semiconductor substrate. This construction suppresses the parasitic capacity of the capacitive element of the MIMC structure. Thus, it is possible to realize a multi-functional high-performance integrated circuit in which the capacitive element of MIMC structure with a low parasitic capacity, the photodiode, and the bipolar transistor are mounted together on the same semiconductor substrate.

Semiconductor device and process for fabrication thereof

A semiconductor device () according to the present invention comprises a vertical PNP bipolar transistor (), an NMOS transistor () and a PMOS transistor () that are of high dielectric strength, and a P-type semiconductor substrate, as shown in FIG.. A substrate isolation layer () of the PNP bipolar transistor (), a drain buried layer () of the NMOS transistor (), and a back gate buried layer () of the PMOS transistor () are formed simultaneously by selectively implanting N-type impurities, such as phosphorous, in the semiconductor substrate (). This invention greatly contributes to curtailing the processes of fabricating BiCMOS ICs and the like including vertical bipolar transistors with easily controllable performance characteristics, such as a current amplification factor, and MOS transistors with high dielectric strength and makes even more miniaturization of such ICs achievable.

Semiconductor device and method of fabricating same

A semiconductor device () according to the present invention comprises a vertical PNP bipolar transistor (), an NMOS transistor () and a PMOS transistor () that are of high dielectric strength, and a P-type semiconductor substrate, as shown in. A substrate isolation layer () of the PNP bipolar transistor (), a drain buried layer () of the NMOS transistor (), and a back gate buried layer () of the PMOS transistor () are formed simultaneously by selectively implanting N-type impurities, such as phosphorous, in the semiconductor substrate (). This invention greatly contributes to curtailing the processes of fabricating BiCMOS ICs and the like including vertical bipolar transistors with easily controllable performance characteristics, such as a current amplification factor, and MOS transistors with high dielectric strength and makes even more miniaturization of such ICs achievable.

Semiconductor device and its manufacturing method

Disclosed is a semiconductor device in which the capacitive element of MIMC structure has a low parasitic capacity. A process for fabrication of said semiconductor device. The semiconductor device has a capacitive element of MIMC structure, a PN photodiode, and a vertical NPN bipolar transistor which are mounted together on the same semiconductor substrate. The lower wiring layer connected to the TiN lower electrode layer of the capacitive element of MIMC structure is formed on the insulating film and the first interlayer insulating film. Between this insulating film and the p-type semiconductor substrate is the p -type low-concentration semiconductor layer whose impurity concentration is lower than that of the p-type semiconductor substrate. This construction suppresses the parasitic capacity of the capacitive element of the MIMC structure. Thus, it is possible to realize a multi-functional high-performance integrated circuit in which the capacitive element of MIMC structure with a low parasitic capacity, the photodiode, and the bipolar transistor are mounted together on the same semiconductor substrate.

A semiconductor device causes less element characteristic fluctuation and hardly causes parasitic actions even when a wire having a barrier metal made of a titanium material is provided. The semiconductor device includes a MOS transistor provided on the surface side of a semiconductor substrate, a first silicon oxide film, a silicon nitride film and a second silicon oxide film provided on the semiconductor substrate while covering the MOS transistor, and a wire having a barrier metal made of titanium material and provided on the insulating film, wherein the silicon nitride film covers the MOS transistor and has an opening on an element isolating region for isolating the MOS transistors. The silicon nitride film is formed in one and the same process as that of a dielectric film of a capacitor element.

Semiconductor device and manufacturing method of the same

A semiconductor device and a manufacturing method therefor which can simultaneously realize both a reduction in base transit time by a reduction in base width and a reduction in base resistance by a reduction in link base resistance. The semiconductor device is manufactured by the method including the steps of forming a first impurity diffused layer of a first conduction type in a semiconductor substrate; forming a conducting film connected to the first impurity diffused layer; forming a first insulating film on the conducting film; forming a first hole through a laminated film composed of the first insulating film and the conducting film; forming a second impurity diffused layer of the first conduction type in the semiconductor substrate exposed to the first hole; forming a side wall from a second insulating film in the first hole to form a second hole; and forming a third impurity diffused layer of the first conduction type in the semiconductor substrate exposed to the second hole.

Growing community of inventors

Kanagawa, Japan

Shigeru Kanematsu