Kabushiki Kaisha Toshiba

Shigeru Kambayashi

Ichiro Mizushima

Yuichiro Mitani

Haruo Okano

Yoshitaka Tsunashima

Yuuichi Mikata

Moto Yabuki

Takako Okada

Shinji Onga

Masahiro Kashiwagi

Kiyotaka Miyano

Hirotaka Nishino

Junichi Wada

Iwao Kunishima

Masami Aoki

Yasuhiko Sato

Takashi Koiso

Naoki Imasaki

Kanako Hattori

A detection system includes a sensitiveness level setup control section and a receiver control section. The sensitiveness level setup control section looks into a sensitiveness level setup file and finds the sequence of levels of sensitiveness to the received signals corresponding to the setup ID. The receiver control section converts, for each component, a sequence of levels of sensitiveness to received signals received from the sensitiveness level switching section into signals for designating levels of sensitiveness to received signals corresponding to the respective receivers, and transmits the signals for designating levels of sensitiveness to received signals through the communication network.

Detection system, detection method, and detection computer program product

A process is provided with which amorphous silicon or polysilicon is deposited on a semiconductor substrate. Then, a low-temperature solid phase growth method is employed to selectively form amorphous silicon or polysilicon into single crystal silicon on only an exposed portion of the semiconductor substrate. A step for manufacturing an epitaxial silicon substrate a exhibiting a high manufacturing yield, a low cost and high quality can be employed in a process for manufacturing a semiconductor device incorporating a shrinked MOS transistor. Specifically, a silicon oxide layer having a thickness which is not larger than the mono-molecular layer is formed on the silicon substrate. Then, an amorphous silicon layer is deposited on the silicon oxide layer in a low-temperature region to perform annealing in the low-temperature region. Thus, the amorphous silicon layer is changed into a single crystal owing to solid phase growth. Thus, a silicon epitaxial single crystal layer exhibiting high quality is formed on the silicon substrate. The present invention is suitable as a process for manufacturing a high-speed and high degree of integration of a semiconductor device having an elevated source/drain structure and a SALICIDE structure.

Method of manufacturing a semiconductor device with oxide mediated epitaxial layer

A process is provided with which amorphous silicon or polysilicon is deposited on a semiconductor substrate. Then, a low-temperature solid phase growth method is employed to selectively form amorphous silicon or polysilicon into single crystal silicon on only an exposed portion of the semiconductor substrate. A step for manufacturing an epitaxial silicon substrate exhibiting a high manufacturing yield, a low cost and high quality can be employed in a process for manufacturing a semiconductor device incorporating a shrinked MOS transistor. Specifically, a silicon oxide layer having a thickness which is not larger than the mono-molecular layer is formed on the silicon substrate. Then, an amorphous silicon layer is deposited on the silicon oxide layer in a low-temperature region to perform annealing in the low-temperature region. Thus, the amorphous silicon layer is changed into a single crystal owing to solid phase growth. Thus, a silicon epitaxial single crystal layer exhibiting high quality is formed on the silicon substrate. The present invention is suitable as a process for manufacturing a high-speed and high degree of integration of a semiconductor device having an elevated source/drain structure and a SALICIDE structure.

Semiconductor device with oxide mediated epitaxial layer

A method of manufacturing a semiconductor device including the steps of forming an insulating film on a silicon region of a substrate having the silicon region on a surface the insulating film having an opening for forming an exposed region of the silicon region, supplying a gas containing a halogen onto the silicon region, and supplying a source gas of silicon onto the silicon region, thereby selectively depositing the silicon on the exposed region of the silicon region.

Semiconductor device and manufacturing method thereof

A single crystal and a polycrystal having an excellent crystal quality and providing a highly reliable semiconductor device are formed by solid phase growth at low temperatures. An amorphous thin film is deposited on a substrate such that an average inter-atomic distance of main constituent element of the amorphous thin film is 1.02 times or more of an average inter-atomic distance of the elements in single crystal, and crystallization energy is applied to the amorphous thin film to perform solid phase growth to thereby form a single crystal. In another embodiment of the present invention, an amorphous semiconductor thin film is formed on a substrate or an insulating film such that an average inter-atomic distance distribution of main constituent element of the film substantially coincides with an average inter-atomic distance distribution of the element in a single crystal, and crystallization energy is applied to the amorphous semiconductor thin film to cause solid phase growth to thereby form a single crystalline semiconductor thin film.

Semiconductor device and its fabricating method

The semiconductor device comprises a semiconductor substrate having an element region, an element isolation film formed on the semiconductor substrate so as to surround the element region, a gate portion crossing the element region and extending over the semiconductor substrate, the gate portion comprising at least a gate insulation film formed on the semiconcuctor substrate and a gate electrode formed on the gate insulation film, and source/drain regions formed on the surface of the element regions on both sides of the gate portion, wherein an upper surface of the element isolation film is formed in substantially the same plane as an upper surface of the gate portion.

Semiconductor device with element isolation film

The present invention provides a method for forming a resist pattern which allows a closest pattern to be formed thus solving a problem of misalignment. A substrate has, on the surface thereof, first and second domains having different reflectivity to first light. A resist covers the first and second domains. The first light illuminates the resist and reflects from the surfaces of the first and second domains. A resist pattern forms in the fashion of self-alignment based on the illuminated and reflected light. The sum of the exposure of the illuminated and reflected light is set above a threshold of exposure by which the resist is sensitized in the first domain and set below the threshold of exposure in the second domain.

Method for forming a resist pattern

A method of manufacturing a semiconductor device includes the steps of forming an insulating film on a silicon region of a substrate having the silicon region on a surface the insulating film having an opening for forming an exposed region of the silicon region, supplying a gas containing a halogen onto the silicon region, and supplying a source gas of silicon onto the silicon region, thereby selectively depositing the silicon on the exposed region of the silicon region.

Growing community of inventors

Kawasaki, Japan

Shigeru Kambayashi