Hitachi, Ltd.

Hitachi Vlsi Engineering Corp.

National Research Institute of Police Science

President of National Research of Police Science

Shigeru Honjo

Nobuyuki Moriwaki

Kiyoshi Inoue

Kazumasa Yanagisawa

Yasuaki Takada

Hisashi Nagano

Katsuro Sasaki

Hideaki Nakamura

Yasuo Seto

Masumi Fukano

Teruo Itoi

Kazumitsu Iura

Koichiro Ishibashi

Shuji Ikeda

Takashi Hashimoto

Toshiaki Yamanaka

Katsuhiro Shimohigashi

Akihiro Shimizu

Yoshio Sakai

Naotaka Hashimoto

Toshiaki Masuhara

Osamu Minato

Eiji Takeda

Takashi Nishida

Shoji Hanamura

Kohji Yamasaki

Mieko Kataoka

Kouichiro Tsuge

An object of the present invention is to obtain an apparatus and a method for the detection of chemical agents which are suitable for detecting sulfur mustard and lewisite 1 and are satisfactory from the viewpoint of the speed of detection of chemical agents, the reduction of the rate of wrong information, the specification of the kinds of the chemical agents, and an unmanned continuous-monitoring apparatus. In the present invention, the detecting apparatus comprises a sample introduction section 1 into which a sample is introduced to be heated, an ionization section 2 in which the sample from the sample introduction section is ionized, a mass spectrometry section 3, and a computer 6 for data analysis. When predetermined signals characteristic of sulfur mustard or lewisite 1 are observed, it becomes possible to specify the sample.

Apparatus and method for detecting chemical agents

An apparatus for detecting a chemical agent, capable of increasing a detection speed of a chemical agent, decreasing a false alarm rate, pinning down the kind of a chemical agent, and meeting specifications for unattended continuous monitoring equipment suitable for detecting sarin or soman. This detection apparatus comprises a sample introduction unit for introducing a sample, an ionizing unit for positively ionizing the sample from the sample introduction unit, a mass spectrometer unit for analyzing ions of the sample, and a computer for analyzing data, and is best suited for identifying a dangerous substance by detecting signals peculiar to chemical agents, such as sarin or soman.

Chemical agent detection apparatus and method

A memory matrix--which comprises memory cells arranged in matrix, each made up of a ferroelectric capacitor and an address selection MOSFET--is divided for each word line into a plurality of memory blocks. Each of the memory blocks is provided with a mode storage circuit that stores a DRAM mode (volatile mode) or an NV mode (non-volatile mode) in one-to-one correspondence for each memory block, and with a refresh operation count circuit that counts for each memory block the number of times the refresh operations is performed consecutively. During an n-th refresh operation (where n is a predetermined number of times), a memory access is made to temporarily change the plate voltage of the ferroelectric capacitor from one voltage to another and at the same time the mode storage circuit is changed from the DRAM mode to the NV mode. When a read or write operation to and from a memory cell in the memory block is performed, the mode storage circuit is changed from the NV mode to the DRAM mode. The refresh operation is omitted for the memory block that was set to the NV mode according to the stored information in the mode storage circuit.

Semiconductor memory device

A memory matrix--which comprises memory cells arranged in matrix, each made up of a ferroelectric capacitor and an address selection MOSFET--is divided for each word line into a plurality of memory blocks. Each of the memory blocks is provided with a mode storage circuit that stores a DRAM mode (volatile mode) or NV mode (non-volatile mode) in one-to-one correspondence for each memory block, and with a refresh operation count circuit that counts for each memory block the number of times the refresh operations is performed consecutively. During an n-th refresh operation (where n is a predetermined number of times), a memory access is made to temporarily change the plate voltage of the ferroelectric capacitor from one voltage to another and at the same time the mode storage circuit is changed from the DRAM mode to the NV mode. When a read or write operation to and from a memory cell in the memory block is performed, the mode storage circuit is changed from the NV mode to the DRAM mode. The refresh operation is omitted for the memory block that was set to the NV mode according to the stored information in the mode storage circuit.

Herein disclosed is a semiconductor integrated circuit device which has a memory array or a memory mat formed of memory cells arranged regularly in a matrix shape. At the end portion or inside of the memory array or memory cell in the region of the device where the patterning of the memory cells is discontinued or interrupted, the shape of an element isolating insulating film, which is formed for regulating the memory cells having pattern interruptions, is made substantially identical to the shape of the element isolating insulating film for regulating the memory cells in the region of the device where the patternings of the memory cells are of an uninterrupted regular form. In the location on the chip front face where the regular patterns associated with the memory area are discontinued, there is formed a dummy pattern having a shape made substantially identical to that of a gate electrode arranged at the end portion of the location where the regular patterns are interrupted.

Semiconductor integrated circuit device having a compact arrangement of

In a semiconductor memory, a latch circuit is arranged between the outputs of a sense amplifier and the inputs of a data output buffer. First pass-gates are arranged between the outputs of the sense amplifier and the latch circuit, while second pass-gates are arranged between the latch circuit and the inputs of the data output buffer. The outputs of the sense amplifier are transmitted to the inputs of the data output buffer through signal paths which bypass the first pass-gates, the latch circuit and the second pass-gates, whereby the data output buffer generates a data output quickly. Thereafter, the first pass-gates and the second pass-gates are controllably brought to a signal-through condition, whereby the output information items of the sense amplifier are stored in the latch circuit. The data output buffer holds the data output in conformity with the stored information items of the latch circuit. For a period of time for which the data output buffer holds the data output, the sense amplifier is held in a non-activated condition, so that the power consumption of the semiconductor memory is lowered.

High speed semiconductor memory having a direct-bypass signal path

A semiconductor static random access memory having a high .alpha.-ray immunity and a high packing density is provided which is also capable of high-speed operation. A semiconductor memory device comprises static random access memory cells each including a flip-flop circuit. Storage nodes of each flip-flop circuit have respective pn-junctions formed at regions sandwiched between gate electrodes of first insulated gate field effect transistors and gate electrodes of second insulated gate field effect transistors, respectively. The pn-junction has an area smaller than that of a channel portion of the first or second insulated gate field effect transistor. The gate electrode of one of the two first insulated gate field effect transistors and the drain region of the other insulated gate field effect transistor, on one hand, and the drain region of the one insulated gate field effect transistor and the gate electrode of the other insulated gate field effect transistor, on the other hand, are electrically cross-coupled mutually through first and second electrically conductive films, respectively. Also, to increase packing density and enhance immunity to soft error, the gate electrodes of the first and second insulated gate field effect transistors extend substantially in parallel with one another and the channel regions of the first and second insulated gate field effect transistors extend substantially in parallel with one another.

Semiconductor memory device having flip-flop circuits

Growing community of inventors

Otsuki, Japan

Shigeru Honjo