Kabushiki Kaisha Toshiba

Sony Corporation

Tokyo Shibaura Denki Kabushiki Kaisha

Shigeru Atsumi

Sumio Tanaka

Hironori Banba

Toru Tanzawa

Tadayuki Taura

Akira Umezawa

Masao Kuriyama

Nobuaki Ohtsuka

Shinji Saito

Junichi Miyamoto

Hitoshi Shiga

Yoshinori Takano

Hidetoshi Saito

Takeshi Miyaba

Keniti Imamiya

Seiichi Mori

Nobuaki Otsuka

Seiji Yamada

Masaki Sato

Yasuo Itoh

Tooru Tanzawa

Yumiko Iyama

Norihisa Arai

Fuminari Tanaka

Daisuke Yoshioka

Koichi Kanzaki

Hidetoshi Yamanaka

Yukinori Muroya

Yasuo Kawahara

Ryo Sudo

Kenji Shibata

Toshiyuki Nishimura

Nobauki Otsuka

Shuji Maeda

Toru Yoshida

A semiconductor memory device able to read out data at a high speed continuously, provided with, corresponding to a plurality of banks, current address registers for holding addresses for reading data of cell arrays, reserved address registers able to receive in advance and hold reserved addresses for next read operations from the outside, and bank control circuits for making the current address registers hold reserved addresses held in the reserved address registers, making the data be read out, and making the data latch circuits hold the data when the data read out from the cell arrays of the banks by addresses held in the current address registers and held in the data latch circuits become able to be transferred to the outside, and a signal processing system relating to the same.

Semiconductor memory device and signal processing system

There are provided a boosted voltage generating circuit and a semiconductor memory device having the boosted voltage generating circuit which includes a booster circuit for outputting high voltage obtained by boosting the power supply voltage, a regulator circuit supplied with the high voltage, for generating voltage whose voltage value is smaller than the value of the high voltage and which is variably set to at least two values based on the high voltage at the operating time, and a equalizer circuit connected to the booster circuit and regulator circuit, for short-circuiting an output node of the booster circuit and an output node of the regulator circuit in response to a first control signal, wherein the operative period of the regulator circuit and the short-circuiting operation period of the equalizer circuit do not overlap each other.

Boosted voltage generating circuit and semiconductor memory device having the same

A semiconductor integrated circuit device includes a main cell array, a fuse cell array, main cell word lines arranged at the main cell array, and fuse cell word lines arranged at the fuse cell array. The fuse cell word lines are formed in a same direction as a direction of the main cell word lines.

Semiconductor intergrated circuit device with a main cell array and a fuse cell array whose word lines and bit lines are extended in the same directions

A semiconductor device at least has a memory cell array. The memory cell array has active regions extending linearly in parallel with one another at predetermined intervals and each containing alternating source and drain regions, gate electrodes orthogonally crossing the active regions between the source and drain regions and each having a floating gate and a control gate laid one upon another, first conductors extending linearly in parallel with the gate electrodes and connected to corresponding ones of the source regions through source contacts, and second conductors connected to corresponding ones of the drain regions through drain contacts.

Semiconductor memory with nonvolatile memory cell array and semiconductor device with nonvolatile memory cell array and logic device

A semiconductor memory device is provided using a sense amp circuitry capable of lowering a supply voltage. The semiconductor memory device includes an array of memory cells each configured to store data in accordance with the presence/absence or the magnitude of a current; a sense amp configured to compare a voltage caused on a sense line based on data in a memory cell selected from the array of memory cells with a reference voltage applied to a reference sense line to determine the data; and a reference voltage generator configured to generate the reference voltage applied to the reference sense line.

Semiconductor memory device and current mirror circuit

A number of transistors including gate oxide films of different thicknesses and an external terminal are formed on a semiconductor substrate. The transistor connected directly to the external terminal is a transistor other than the transistor having the thinnest gate oxide film. That is, a node which is in contact with an external power supply and thus requires a high breakdown voltage is formed of a thick gate oxide film transistor, while a node which is not in contact with the external power supply is formed of a thin gate oxide film transistor. With this structure, a number of transistors including gate oxide films of different thicknesses can be integrated in a single chip without deterioration of the transistor characteristics. Hence, the degree of freedom with which to design devices/circuits can be remarkably enhanced.

Semiconductor integrated circuit device and flash EEPROM

A semiconductor device has an address counter to output, in a first mode, a first block address whereas, in a second mode, a second block address selected from a block-address space two times larger than a block-address space corresponding to memory blocks, the memory blocks and at least one redundant block being included in a memory section, and a block-selection controller, in the second mode, one of the memory blocks, which corresponds to the output of the address counter, when the most significant value of the second block address as the output of the address counter is at a first level whereas select the redundant block while the memory blocks are inhibited from selection, when the most significant value is at a second level.

Semiconductor device including semiconductor memory

A non-volatile semiconductor memory comprises a memory cell array having a plurality of non-volatile memory cells, at least one reference cell, a read circuit for reading data by applying a first voltage to one of word lines to compare a current flowing through one of bit lines with a current flowing through the reference cell, an erase circuit for erasing the data by applying a voltage to at least two selected from the word lines, the bit lines, the source lines and a semiconductor region including the memory cells, first and second regulators, and an erase verify circuit for detecting whether the erase has finished by applying an output voltage of the first regulator to word lines of the memory cells to be erased, while applying an output voltage of the second regulator to a word line of the reference cell, thereby comparing a cell current of selected one of the memory cells with a cell current of the reference cell.

Non-volatile semiconductor memory

A semiconductor integrated circuit device includes fuse cells arranged at a fuse cell array, a fuse cell data program and erase circuit, a fuse cell data control circuit, and fuse data latch circuits. The fuse cells include erasable and programmable nonvolatile memory cells. The fuse cell data program and erase circuit programs fuse data to the memory cells and erases the fuse data from the memory cells. The fuse cell data control circuit controls read out timing of the fuse data stored in the memory cells based on a signal generated upon detection of power-on. The fuse data latch circuits latch the fuse data read out from the memory cells.

Semiconductor integrated circuit device with erasable and programmable fuse memory

A nonvolatile semiconductor memory device includes a first memory cell array including electrically re-programmable main memory cells, a second memory cell array including electrically data-programmable redundancy memory cells, a first storage configured to store a specified code, a first comparator configured to compare a selected code with the specified code to generate an activating signal, a faulty address latch circuit configured to be activated by the activating signal and controlled to temporarily latch a fault address corresponding to the fault, a second storage configured to store the faulty address latched by the faulty address latch circuit, a second comparator configured to compare an input address with the faulty address to generate a replacement control signal when the input address coincides with the faulty address, and a replacing circuit configured to replace an output of the first memory cell array with an output of the second memory cell array.

Nonvolatile semiconductor memory device and method of retrieving faulty in the same

A semiconductor integrated circuit device includes first to fourth bit lines and a redundant bit line, first to fourth column gate transistors and a redundant column gate transistor coupled to each of the first to fourth bit lines and the redundant bit lines, first to fourth column select lines and a redundant column select line coupled to each of the first to fourth column gate transistors and the redundant column gate transistor. The second column select line passes through the first bit line. The third column select line passes through the first and second bit lines. The fourth column select line passes through the first, second and third bit lines. The redundant column select line passes through the first, second, third and fourth bit lines.

Fast data readout semiconductor storage apparatus

The semiconductor memory comprises a reference current generator, first and second current converters, sense amplifiers for read, and sense amplifiers for verify. The reference current generator generates a first voltage dependent upon the current flowing through a reference cell. The first current converters, to which the first voltage is input, each generate a second voltage. The second current converters, to which the first voltage is input, each generate a third voltage. The sense amplifiers for read output data of a selection memory cell, comparing the voltage of the data-line for read with the second voltage. The sense amplifiers for verify output verify data of the selection memory cell, comparing the voltage of the data-lines for verify and the third voltage.

Nonvolatile semiconductor memory having page mode with a plurality of banks

Growing community of inventors

Yokohama, Japan

Shigeru Atsumi