Kabushiki Kaisha Toshiba

Shigeo Oshima

Haruki Toda

Naoki Matsumoto

Tatsuo Ikawa

Hiroshi Sahara

In a semiconductor integrated circuit, the wiring capacitance of the bus line region is reduced, so that the operation speed can be increased, the power consumption can be decreased, and the chip size can be reduced. On the upper surface of the field oxide film (4) formed on the semiconductor substrate (8), a non-conductive insulating oxide film (12) is formed by oxidizing the poly silicon layer (9). Further, the bus lines (3A) are formed on the oxide film (12) via the interlayer insulating film (6). Therefore, a distance between the bus lines (3A) and the substrate (8) can be increased to decrease the capacitance of the bus lines (3A).

Semiconductor integrated circuit having reduced wiring capacitance

A multiport memory comprises a pair of memory cells, at least a pair of bit line and a pair of word lines on a random access port side. One of the memory cell is connected to one bit line and one word line and the other memory cell is connected to the other bit line and the other word line. A pair of data lines which are respectively connected to load elements are also provided in the random access port side of the multiport memory. A first switch circuit is connected between the pair of bit lines and the pair of data lines. On a serial access port side, a data register is connected between the pair of bit lines to receive data transmitted through the pair of bit lines. A second switch circuit for transmitting data is connected between the pair of bit lines and the data register. A control circuit opens the first switch circuit, before closing the second switch circuit to transmit data stored in the memory cells to the data register.

Multiport memory

In a semiconductor memory system of the serial column access type, a redundant column is used for replacing a defective column. Redundant data lines are connected to the redundant column through a redundant column selection gate. A defective address detection circuit detects the address of a defective column to enable the redundant column selection gate. An address counter is provided for a defective address detection circuit. A redundant column selection circuit selects the redundant column in response to a detection signal from the defective address detection circuit. A data line switching circuit switches, in redundant column select mode, the data lines connecting to a data input/output drive circuit from said regular data lines to the redundant data lines. With this circuit arrangement, in a redundant column select mode, the regular data lines are separated from the data input/output drive circuit. Therefore, even if a shift register constituting a regular column selection circuit operates and the defective column selection gate is enabled to set up a connection of the defective column to the regular data lines, the error data from the defective column is never output. Further, the shift register is operable irrespective of the defecting column detection.

Growing community of inventors

Yokohama, Japan

Shigeo Oshima