Sharp Kabushiki Kaisha Corporation

Shigeo Onishi

Keizo Sakiyama

Kenichi Tanaka

Kazuya Ishihara

Akitsu Ayukawa

Jun Kudo

Hiroshi Ishihara

Yasuyuki Itoh

Seiichi Yokoyama

Hidehisa Tateoka

Yasushi Kubota

Yoshimitsu Yamauchi

Katsuji Iguchi

Toshiyuki Okumura

Yasuyuki Ito

Takao Kinoshita

Kazuyo Nakamura

Satoru Yamagata

Tatsushi Yusuki

Masato Kawai

Osamu Yamazaki

Masaya Komai

Keiichiro Uda

Tsutomu Yamadai

Hiromi Hattori

Nobutaka Fukushima

Hitoshi Urashima

In a semiconductor device producing method, a plug is formed within a contact hole formed in a barrier film and an interlayer insulating film on a semiconductor substrate. Then, an insulation film is formed on the plug and barrier film, and a hole is made in the insulation film such that an upper surface of the plug is exposed. A first conductive film is formed on the insulation film so as to fill the hole, and then etched by a CMP method to form a lower electrode within the hole. The insulation film is removed and the lower electrode is left in a protuberant manner. A dielectric film made of a ferroelectric or high-dielectric-constant substance and a second conductive film are sequentially formed over the lower electrode and the barrier film, and then patterned simultaneously to thereby form a capacitor dielectric film and an upper electrode.

Semiconductor device producing method and semiconductor device

In a semiconductor memory device, a tantalum silicon nitride film or hafnium silicon nitride film is provided, as a diffusion barrier layer, between a polysilicon plug which electrically connects a source/drain region to a lower platinum electrode of a capacitor, formed on a silicon substrate, and the lower platinum electrode. The tantalum silicon nitride film has a composition of Ta.sub.X Si.sub.1-X N.sub.Y wherein 0.75 .ltoreq.X.ltoreq.0.95 and 1.0 .ltoreq.Y.ltoreq.1.1. The hafnium silicon nitride film has a composition of Hf.sub.X Si.sub.1-X N.sub.Y wherein 0.2&lt;X&lt;1.0 and 0&lt;Y&lt;1.0.

Semiconductor memory device with amorphous diffusion barrier between

A titanium film and a titanium nitride film are sequentially formed on a polysilicon plug. Next, the titanium nitride film is oxidized to form an oxidized titanium nitride film. Thereafter, a lower electrode and a PZT film are formed. A diffusion barrier layer is prepared from the oxidized titanium nitride film and is oxidized before the lower electrode is formed. As a result, unlike in prior art, the diffusion barrier layer is not oxidized after the lower electrode is formed. Peel-off between the diffusion barrier layer and the lower electrode due to the oxidation is thus prevented.

Manufacturing method of electrode

A process for fabricating a nonvolatile semiconductor memory device has one transistor and one ferroelectric capacitor electrically connected to each other by a contact plug, which comprising forming a transistor; forming an inter-layer insulating film, at least an upper surface portion thereof being a titanium oxide film; forming a capacitor lower electrode; and forming a capacitor insulating film and a capacitor upper electrode, wherein the lower electrode forming step comprises: depositing a titanium nitride film and a platinum film on the titanium oxide film; etching the platinum film with a first etching gas adapted to suppress deposition of substances including platinum; and etching the titanium nitride film with a second etching gas having a high etching selectivity to the titanium oxide film.

Process for fabricating nonvolatile semiconductor memory device having a

A method for etching a ferroelectric film made of a compound containing lead of the present invention, includes the steps of: forming an insulating film, metal films, and a ferroelectric film on a substrate in this order; forming an etching resistant film on the ferroelectric film, followed by patterning; and etching the ferroelectric film with a mixed gas containing an inert gas and a halogen gas or a halogenated gas as an etching gas, using the patterned etching resistant film as an etching mask.

Method for etching ferroelectric film

A non-volatile random access memory comprises a memory cell including: a MOS transistor having a gate insulation film formed on a semiconductor substrate, a gate electrode, and a pair of impurity diffusion layers; and an MFS transistor having at least a bottom gate electrode, a ferroelectric film, a top electrode, and a pair of impurity diffusion layers, one of the impurity diffusion layers of the MFS transistor being shared with the MOS transistor and connected to a portion of the bottom gate electrode; wherein the MOS transistor is connected to a bit line and a word line, and the MFS transistor is connected to a drive line and a common source line.

Non-volatile random access memory

A non-volatile random access memory comprises an MOS transistor having a gate insulation film formed on a semiconductor substrate, a gate electrode formed on the gate insulation film, and a pair of diffusion layers formed in the semiconductor substrate; and a ferroelectric capacitor having a bottom electrode connected to one of the diffusion layers of the MOS transistor, a capacitor ferroelectric film formed only on the bottom electrode, and a top electrode formed on the capacitor ferroelectric film; wherein at least side walls of the bottom electrode and the capacitor ferroelectric film are coated with lamination of a diffusion prevention film and a thin insulation film; an upper surface of the capacitor ferroelectric film is contacted with the top electrode; the other diffusion layer of the MOS transistor is connected to a bit line; the gate electrode is connected to a word line; and the top electrode of the ferroelectric capacitor is constituted so as to serve as a drive line.

Non-volatile random access memory and fabrication method thereof

A method for etching a Pt film of the present invention includes the steps of: forming an etching resistant film on a Pt film, followed by patterning; etching the Pt film by using as an etching mask the etching resistant film and by using, as an etching gas, a mixed gas containing oxygen gas and chlorine gas or chloride gas, during which layers made of PtCl.sub.x O.sub.y or a mixture containing PtCl.sub.x and PtO.sub.y are formed on side walls of the etching resistant film and the Pt film; and removing the layers made of PtCl.sub.x O.sub.y or the mixture containing PtCl.sub.x and PtO.sub.y with an acid by wet etching after the etching step.

Method for etching PT film

A lower capacitor electrode is formed on the basic plate 1, and thereafter a ferroelectric film, for example, a PZT film having the Pb is formed. ITO, RuO2, SnO2 which are Pt or oxide conductive material are formed as a cap layer into 200 .ANG. or more in film thickness by a sputtering method or silicone oxide film or the like are formed with 200A or more in film thickness by a thermal CVD method. Thereafter, a thermal operating operation is effected. By the prevention of the Pb from being evaporated at the thermal processing time, the elaborate ferroelectric film of stoichiometrical perovskite construction can be formed.

Crystallizing method of ferroelectric film

The disclosed invention is a process for fabricating a semiconductor device comprising the steps of:

Process for producing semiconductor device comprising two step annealing

Random access memory includes a pair of metal oxide semiconductor (MOS) transistors which are connected to each other by a common impurity diffusion region, and a capacitor which is formed of ferroelectric film acting as a capacitor layer and is connected to the impurity diffusion region, one of the pair of MOS transistors being connected to a bit line and a word line.

Non-volatile random access memory with ferroelectric capacitor

A ferroelectric memory device according to the present invention comprises a plurality of bit lines carrying data signals and voltage signals, every adjacent two of the bit lines being paired to form a plurality of bit line pairs; sense amplifiers connected to each of the bit line pairs; a plurality of memory cells for storing data, each memory cell having a first capacitor and a first switching element, the first capacitor being connected to one of the bit lines via the first switching element, wherein the first capacitor includes a capacitor insulating film, at least one portion of the capacitor insulating film being formed of a ferroelectric material; a plurality of dummy cells for storing a reference voltage, each dummy cell having a second capacitor and a second switching element, the second capacitor being connected to one of the bit lines via the second switching element, wherein the second capacitor includes the capacitor insulating film at least one portion of the capacitor insulating film being formed of a ferroelectric material; a first common electrode line for controlling a voltage to be applied to the first capacitor; a second common electrode line for controlling a voltage to be applied to the second capacitor; a first word line for controlling the first switching element; and a second word line for controlling the second switching element, wherein a plurality of the memory cells and at least one of the dummy cells are connected to each bit line.

Driving circuit of a ferroelectric memory device and a method for

A non-volatile random access memory comprising a plurality of unit cells each of which includes; a transistor composed of source/drain and gate electrodes, a ferroelectric capacitor connected to either of the source/drain electrodes and a high load device connected to both of the ferroelectric capacitor and the source/drain electrodes being connected to the ferroelectric capacitor.

Non-volatile random access memory having a high load device

A method of forming a ferroelectric film on a heated support is provided which includes the steps of forming a first layer on the heated support by sputtering a material including lead at a first pressure; and forming a second layer on the first layer by sputtering the material at a second pressure, the second pressure being lower than the first pressure.

Method of forming a ferroelectric film

A dynamic random access memory includes a plurality of DRAM cell units having a bit contact region and DRAM cells formed on an active region, wherein the DRAM cells each comprised of a transistor and a capacitor connected to the transistor are arranged symmetrically to the right and left sides in a bit contact connected with the active region to form the DRAM cell unit; and the DRAM cell units are arranged with a prescribed pitch in the direction of X and arranged in the direction of Y shifted with one third of the pitch toward the direction of X.

Growing community of inventors

Nara, Japan

Shigeo Onishi