Kabushiki Kaisha Toshiba

Shigeo Ohshima

Haruki Toda

Hiroshi Sahara

Hiroyuki Ohtake

Kazuaki Kawaguchi

Tatsuo Ikawa

Naoya Tokiwa

Katsumi Abe

Koji Hosono

Takuya Futatsuyama

Kazushige Kanda

Toshiaki Edahiro

Nobuo Watanabe

Koji Kato

Masahiro Kamoshida

Katsushi Nagaba

Shinji Miyamoto

Masakazu Kiryu

Kiminobu Suzuki

Mie Matsuo

Satoru Takase

Yuui Shimizu

Noriyasu Kumazaki

Eiichi Makino

Keiji Maruyama

Koichi Magome

Kazuko Inuzuka

Susumu Ozawa

Kiyoaki Iwasa

Kazuhiro Yamada

Donald C Stark

Tohru Furuyama

Makoto Segawa

Yuji Watanabe

Naoki Matsumoto

Natsuki Kushiyama

Naohisa Okumura

Yasuhiro Suematsu

Kiyofumi Sakurai

Hiroyuki Koinuma

Yoshinori Ogawa

Hiroyuki Noji

Youichi Suzuki

Satoshi Yamano

Kenji Komatsu

Yasuyuki Kai

Takamichi Arizono

Takehiro Hasegawa

Katsuji Tokonami

Yuji Wtanabe

A semiconductor device, a semiconductor memory tester, and a multi-chip package are provided. The semiconductor device includes a plurality of nonvolatile semiconductor memories; a boosting circuit which generates a boosted voltage for operating the plurality of nonvolatile semiconductor memories; and a boosting circuit controller which controls the operation of the boosting circuit to generate the boosted voltage on the basis of an operation sequence of the plurality of nonvolatile semiconductor memories.

Semiconductor device and semiconductor memory tester

The present invention provides a method for writing data to a non-volatile memory device having first wirings and second wirings intersecting one another and memory cells arranged at each intersection therebetween, each of the memory cells having a variable resistive element and a rectifying element connected in series. According to the method, the second wirings are charged to a certain voltage not less than a rectifying-element threshold value, prior to a rise in a selected first wiring. Then, a selected first wiring is charged to a voltage required for writing or erasing, after which a selected second wiring is discharged.

Non-volatile memory device and method for writing data thereto

A memory may include word lines; bit lines; cells provided corresponding to intersections between the word lines and the bit lines; sense amplifiers detecting data; a column decoder selecting a certain bit line for the sense amplifiers to output read data or receive write data; a row decoder configured to select a certain word line; a charge pump supplying power to the sense amplifiers, the column decoder, and the row decoder; a logic circuit controlling the sense amplifiers, the column decoder, and the row decoder based on an address selecting the memory cells; a first power source input applying a voltage to the logic circuit; and a second power source input applying a voltage higher than a voltage of the first power source input to the charge pump, and to supply power to the charge pump at least at a data reading time and a data writing time.

Nonvolatile semiconductor memory device and nonvolatile semiconductor memory system

A method of programming a non-volatile memory device with memory cells formed of variable resistance elements and disposed between word lines and bit lines, includes: previously charging a selected word line and a selected bit line together with a non-selected word line and a non-selected bit line up to a certain voltage; and further charging the selected word line and the non-selected bit line up to a program voltage higher than the certain voltage and a program-block voltage, respectively, and simultaneously discharging the selected bit line.

Method of programming a non-volatile memory device

A layout-data generation equipment includes a logic circuit designing section which designs a logic circuit based on information of the specifications of a semiconductor integrated circuit, a layout-data generation section which creates layout-data based on the logic circuit, a resistance information extraction section which extracts resistance information of a wire from the layout-data, a circuit simulation execution section which executes a circuit simulation, an identification section of current direction which identifies a direction of a current in the wire based on the resistance information of a wire and an execution result of the circuit simulation, a verification section which verifies whether layout-data of the wire breaks a design rule, the design rule being extracted from the information of the specifications of a semiconductor integrated circuit and the verification section generates this verification result, and a data output section which outputs the layout-data.

Layout data generation equipment of semiconductor integrated circuit, data generation method and manufacturing method of semiconductor device

According to one embodiment, a nonvolatile memory device includes: a memory cell array including memory cells each having a variable resistance element for nonvolatilely storing data identified by an electrically rewritable resistance value; a first data latch storing write and erase data to be written on a given group of memory cells of the memory cell array for a write and erase operation; and a second data latch storing reference data for performing a compensation operation of the given group to compensate write and erase disturbance accompanied by the write or erase operation.

Non-volatile memory device

This disclosure concerns a memory including: word lines extending to a first direction; bit lines extending to a second direction crossing the first direction; a memory cell array including cell blocks each including memory cells respectively provided corresponding to intersection points of the word lines and the bit lines; and sense amplifiers provided corresponding to the bit lines, wherein the sense amplifiers copies existing data stored in a first cell block within the memory cell array to a plurality of memory cells, the memory cells being included in second and third cell blocks different from the first cell block, and alternately arranged in an extension direction of the word lines and also alternately arranged in an extension direction of the bit lines, and the sense amplifiers reads data from the second cell block or the third cell block, at a time of outputting data to outside of the sense amplifiers.

Semiconductor memory device and driving method thereof

The verification equipment of a semiconductor integrated circuit in the present invention is included with a circuit net list extraction section that extracts the net list of a circuit, a circuit simulation execution section that executes a circuit simulation, based on the extracted net list, a finite impedance judgment section that judges existence or nonexistence of finite impedances, a floating error terminal judgment section that judges existence or nonexistence of floating error terminals by measuring finite impedances, a true floating error terminal judgment section that adds any one of a P channel-type transistor and an N channel-type transistor to terminals of the circuit where it is judged that there are floating error terminals and calculates changes in potential at the terminals and adds the other of the P channel-type transistor and the N channel-type transistor to the terminals and calculates changes in potential at the terminals, and an output section that outputs a judgment result of the floating error terminal judgment section and a judgment result of the true floating error terminal judgment section.

Verification equipment of semiconductor integrated circuit, method of verifying semiconductor integrated circuit and process of manufacture of semiconductor device

A semiconductor device including a circuit substrate including n number of terminals; a semiconductor chip provided on the circuit substrate and including n number of terminals; and a relay chip including a triangular substrate having a first side, a second side and a third side which form triangle, n number of first terminals located along the first side, n number of second terminals located along the second side, and a plurality of wires connecting the first terminals and the second terminals respectively; a first wire connecting each of the n number of terminals of the circuit substrate to a corresponding first terminal among the n number of first terminals; and a second wire connecting each of the n number of terminals of the semiconductor chip to a corresponding second terminal among the n number of second terminals.

Semiconductor device, relay chip, and method for producing relay chip

This disclosure concerns a device outputting data to the outside comprising a first transistor with a first conductive type which is connected between an output low voltage corresponding to a first logical value and the pad and which connects the output low voltage to the pad when the digital data has the first logical value; a second transistor with a second conductive type which is connected between an output high voltage corresponding to a second logical value and the pad and which connects the output high voltage to the pad when the digital data has the second logical value; and a third transistor with the first conductive type which is connected between the output high voltage and the pad so as to be parallel to the second transistor and which connects the output high voltage to the pad when the digital data has the second logical value.

Semiconductor integrated circuit device

In an FCRAM having a late write function, when a first command signal indicates 'write active', whether a write operation or an auto-refresh operation is to be performed is determined on the basis of a second command signal. For example, when the second command signal indicates 'write', a write operation for a memory cell is performed by a late write scheme. When the second command signal indicates &#x201c;auto-refresh&#x201d;, an auto-refresh operation is performed. In the last write cycle of a write operation immediately preceding this auto-refresh operation, addresses for selecting a memory cell as an object of auto-refresh are predetermined. After data write to a memory cell is completed in the last write cycle, row precharge for auto-refresh is performed. After that, an auto-refresh operation (i.e., a data read operation and a data restore operation) is performed for the selected memory cell.

Synchronous semiconductor memory

An input data register for latching write data is arranged in a position near a memory cell array of a memory core section. The input data register is arranged on the upstream side of a data path used for writing data into a memory cell. Write data input to a data pin which is arranged in the end position on the downstream side is latched in the input data register via a data input buffer, serial/parallel converting circuit and write data line. Data latched in the input data register is written into a memory cell via a DQ write driver, data line pair, I/O gate and bit line pair in a next write cycle.

Method for writing data to a semiconductor memory comprising a peripheral circuit section and a memory core section including a memory cell

A synchronous semiconductor memory device includes a plurality of memory banks which read data from memory cells and write data into the memory cells, a command decoder circuit which receives a command, detects whether the command is a read command or a write command, and, when detecting a read command or a write command, outputs a first control signal that enables a read operation or a write operation in the plurality of memory banks, bank select circuits which activate a second control signal to activate each of the memory banks, and bank timer circuits which deactivate the activated second control signal and perform control in such a manner that the timing with which the second control signal is deactivated in a test mode differs from that in a normal mode.

Synchronous semiconductor memory device with a plurality of memory banks and method of controlling the same

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Yokohama, Japan

Shigeo Ohshima