Hitachi, Ltd.

Hitachi Microcomputer Engineering, Ltd.

Hitachi Microcomputer Eng. Ltd.

Shigeo Nishita

Kazuo Yamakido

Tohru Kazawa

Masaru Kokubo

Takahiko Kozaki

Takanori Miyamoto

Takashi Morita

Ichiro Masse

Souichi Yamashita

Toshiroh Suzuki

Kenichi Ohwada

Eiichi Amada

Ryozo Yoshino

Masato Hirai

Clock timing is extracted from N level, multilevel codes of megabits per second data by determining a baud clock among the N-1 possible clocks synchronized to all the level cross points. A discriminator is used with a clock and if correct information is not obtained, the clock is changed.

Timing extraction method and communication system

A PLL circuit for generating an AC output signal synchronized with an AC input signal applied thereto with a phase offset with respect to the input signal includes, in one embodiment, a charge pump circuit capable of varying the phase offset depending on the frequency of the AC input signal. In a signal transmission network system including a plurality of nodes coupled to a signal transmission line and distanced from one another by various repeat lengths of transmission path, each node has a repeater including such PLL circuit to suppress jitter caused by individual repeat length of transmission over the transmission line and still remaining in an equalized AC signal in each node.

Repeater and PLL circuit

A CODEC including a coder and decoder to construct the subscriber's circuit of a digital telephone switching system or the like, wherein an analogue balancing circuit is provided between the output terminal of a post-filter and the input terminal of a pre-filter in order to effectively eliminate a return signal in the case of two-wire/four-wire conversion, and return signals not eliminated by the analogue balancing circuit are further eliminated by a digital balancing circuit. Especially in the present invention, the analogue balancing circuit is so constructed that its characteristics are independent of frequencies, and hence, the analogue balancing circuit and the digital balancing circuit are readily implemented as an LSI.

PCM coder and decoder having function of two-wire/four-wire conversion

A PCM coder and decoder circuit for use in a subscriber line interface circuit of a telephone communication system has a digital balancing network for removing any echo signal. The digital balancing network is formed by series-connecting a first balancing circuit having characteristics corresponding to the fixed characteristics of a coder, decoder, etc. and a second balancing circuit having characteristics corresponding to variable characteristics of an external circuit including two-wire transmission line which is connected to the coder and decoder circuit. Thus, a replica of an echo signal is precisely produced, and the circuit configuration is simplified.

PCM coder and decoder circuit having digital balancing network

An oversampling type digital-to-analog converter which has a light gradient overload and a high signal-to-noise ratio in spite of a comparatively low sampling frequency. In a digital-to-analog converter wherein the difference between an oversampled digital input signal and a feedback signal is taken, such differences are integrated, the integral value is quantized to obtain the feedback signal, and part of the feedback signal is used as an analog output signal; a circuit for the quantization is constructed of a circuit which converts the integral value into a digital signal smaller in the number of bits than the digital input signal, and the feedback signal is obtained by integrating the outputs of the quantization circuit by means of a digital integral circuit.

Interpolative D/A converter

Disclosed is a PCM coder-decoder having a construction such that a digital filter contained originally in the PCM coder-decoder is utilized on the time division basis in order to fold back a digital reception signal to a digital signal transmission side and thus to accomplish interruption, communication exchange between three parties, gain control, fold-over test of the PCM signal, and so forth, in addition to the coding and decoding functions inherent to the PCM coder-decoder.

Growing community of inventors

Kokubunji, Japan

Shigeo Nishita