Hitachi, Ltd.

Hitachi Vlsi Engineering Corp.

Shigeo Kuroda

Masao Kawamura

Kanji Otsuka

Takeo Shiba

Hisashi Nakamura

Yoichi Tamaki

Akihisa Uchida

Kazuhiko Sagara

Toshihiko Takakura

Mikinori Kawaji

Kunizo Sahara

Toshiyuki Sakuta

Kazuya Ito

Takayuki Uda

Makoto Homma

Masanori Tazunoki

Tasuku Tanaka

Yoshiaki Emoto

Toshihiko Satoh

Minoru Enomoto

Hinoko Kurosawa

Keiji Sasaki

Hiromitsu Mishimagi

Takeo Yamada

Mitsuo Usami

Yutaka Watanabe

Katsuyuki Sato

Fumiyuki Kobayashi

Akio Yasukawa

Takayuki Okinaga

Takahiko Takahashi

Masao Sekibata

Masao Kato

Takashi Kumagai

Yuuji Shirai

Seiji Miyamoto

Hiroshi Tachi

Shinichi Shouji

Akio Anzai

Shigejiro Sekine

Kazutoshi Kubo

Masayuki Kawashima

To achieve higher packaging density and one wafer level for a full-sized wafer memory, or wafer-scale integration memory system, the wafers are vertically stacked with each other at a predetermined interval. A packaging technique is improved in such a way that a memory system layout can be precisely realized and a precise through hole can be formed. Moreover, other chips are fixed on the wafer so as to achieve furthermore the high packaging density.

Wafer scale or full wafer memory system, packaging method thereof, and

A method of manufacturing a semiconductor integrated circuit device wherein a conductor film is formed on a front surface of a substrate by a lift-off technique; comprising forming a first resist film on that area of the substrate surface on which the conductor film is not formed, forming a second resist film on the whole substrate surface including the first resist film and a conductor film forming area of the substrate surface, providing a first opening for forming the conductor film in a conductor film forming area of the second resist film and also providing a second opening for forming a dummy conductor film in that area of the second resist film in which the conductor film is not formed, depositing the conductor film on the whole substrate surface including the substrate surface inside the first opening, the first resist film inside the second opening and the second resist film, and removing the second resist film and the first resist film respectively, so as to leave the conductor film inside the first opening and to remove the conductor film on the second resist film and the dummy conductor film on the first resist film.

Method of manufacturing semiconductor integrated circuit device

Wafer scale of full wafer memory system, packaging method thereof, and

A bipolar type of semiconductor integrated circuit device is provided with U-shaped grooves which are formed by cutting a main surface of a semiconductor body to form isolation regions between bipolar transistors. A silicon oxide film can be formed in the U-shaped grooves by thermal oxidation simultaneously with the formation of a silicon oxide film used to form isolation regions between each collector contact region and base region. No separate step is needed for forming the silicon oxide film between the collector contact region and the base region. The thickness of the silicon oxide film can be controlled, and has a sufficient thickness even at its two edges, i.e., at its boundaries with the U-shaped grooves, so that the bipolar transistors exhibit good electrical characteristics. Namely, the collector resistance thereof does not increase, and the breakdown voltage at the pn junction between the collector region and the base region does not decrease. The U-shaped grooves can each comprise narrow and deep sub-grooves, with thick oxide films formed on the surfaces of the sub-grooves and a thick oxide film formed on a surface of an area between the sub-grooves, and with wiring formed on the oxide on the area between the sub-grooves.

Process of manufacturing semiconductor integrated circuit device having

Attempts have been made to increase the number of pins of packages accompanying the trend toward fabricating integrated circuits highly densely and in smaller sizes. The present invention provides technology for improving reliability in fabricating packages of the surface-mounted type that have increased number of pins. That is, when the packages are mounted on the wiring substrate, the lead pins that receive load from the axial direction exhibit bending strength which is smaller than the junction strength of solder at the junction portions. To achieve this object, the lead pins are made of a material having large resiliency such as a fiber-reinforced material, a transformation pseudo elastic material, an ultra-high tension material, or a heat-resistant ultra-high tension material.

Semiconductor device having leads for mounting to a surface of a printed

Process of manufacturing semiconductor integrated circuit device and

The present invention discloses a suitable mounting of a wafer scale LSI (wafer scale integration) (WSI) in which a slit formed in a wafer is fit to a connector, a U-shaped reinforcing rubber member is disposed at the circumferential edge of the wafer, or a flexible adhesive is used for bonding a substrate formed with through-holes and a wafer, to provide a WSI mounting structure of high integration degree and high reliability. Furthermore, a method of efficient mounting by conducting the wiring of the wafer and the connection with the external terminal of the chip in one identical production step is disclosed.

Semiconductor device and method of mounting the semiconductor device

Semiconductor IC with dual groove isolation

An electric component part has its lead terminals bent in thickness directions in a middle section thereof at least two positions so that a step section virtually in parallel to the bottom of a circuit substrate is formed with the intention of absorbing the external force applied to the part by chaging the shape of the lead terminals. Increase in the part layout area due to the formation of the horizontal step section can be avoided, when necessary, by shifting the terminal lead out position on the component part inward thereby to minimize the jetty dimensions.

Electric component part having lead terminals

A method of fabricating semiconductor integrated circuit devices having a semiconductor region in a position separated by a predetermined distance from a dielectric isolating region provided on the surface of a semiconductor wafer, comprising the steps of forming a first mask to define the dielectric isolating region and semiconductor region, forming a second mask over the first mask so as to cover the region which is to become the semiconductor region, and removing the second mask after the dielectric isolating region has been formed by the first and second masks, to form the semiconductor region. The method thus permits the semiconductor region to be self-aligned with the dielectric isolating region.

Method of fabricating semiconductor integrated circuit devices

Growing community of inventors

Ohme, Japan

Shigeo Kuroda