Hitachi, Ltd.

Hitachi Engineering Co., Ltd.

Hitachi Haramachi Electronics Co., Ltd.

Shigeo Kuboki

Ikuro Masuda

Kazuo Kato

Yoji Nishio

Masahiro Iwamura

Takao Sasayama

Norihiko Sugimoto

Masahiro Ueno

Kazuhisa Inada

Toshihiko Tominaga

Hideo Maejima

Hideo Nakamura

Nobuaki Miyakawa

Takeshi Hirayama

Tomoaki Aoki

Takeshi Harakawa

Terumine Hayashi

Akihiko Takano

Shunji Inada

Hiroshi Ichige

Eiki Kondoh

Takamasa Fujinaga

Yoshiaki Ajima

Syunji Inada

Satoko Iwama

Isao Saitoh

Yoshinori Atsuwata

Yoshiaki Homitsu

Mitsuhiro Ikeda

Toshiaki Masuda

The communication control device allows a plurality of data items to be transferred to and from external devices, such as a CPU and a memory, via an external bus having a different data bus width in DMA (direct memory access) transfer mode. DMA transfer is controlled by the DMA controller provided in the communication control device. The DMA controller produces a signal indicating that a plurality of data items are continual.

Communication control device and a communication system using the same

In a data communication adapter apparatus for a digital data communication connected between a signal transmission path for transmitting both receive data and transmit data, and a host processor unit for producing frame data to output the frame data therefrom, an internal host bus is newly employed in the data communication apparatus irrelevant to the employment of a CPU dedicated bus, and the transmission/reception data generated and interpreted by the host processor is transferred via the internal host bus, a bus interface, and a system data bus between a transmission memory or a reception memory and a buffer memory. Furthermore, a reception memory (host dedicated reception memory) for storing only the reception data to be interpreted by the host processor is separately provided with another reception memory (CPU dedicated reception memory) for storing only the reception data to be interpreted by a CPU, one reception data to be interpreted by the CPU is once transferred from the transmission/reception control unit to the CPU dedicated memory and thereafter read out via the CPU dedicated bus under the control of the CPU, and the other reception data to be interpreted by the host processor is one stored in the host dedicated reception memory and then read out via the internal host bus and bus interface under the control of the host processor.

Data communication adapter and data communication terminal apparatus for

A high-speed operation, low-power consumption gate circuit structure comprises a combination of complementary field-effect-transistors and bipolar transistors and discharge means for discharging accumulated charges from these transistors when the field-effect-transistors and bipolar transistors are turned off.

Gate circuit of combined field-effect and bipolar transistors

A high speed and low power consumption semiconductor integrated circuit device has a plurality of internal circuits each including circuit elements for performing a desired circuit operation, a plurality of input circuits for receiving external input signals and supplying the signals to the internal circuits and a plurality of output circuits for receiving the output signals from the internal circuits and supplying signals to an external circuit. Each of the internal circuits is primarily constructed by bipolar transistors and MOS transistors, and at least one of each of the input circuits and each of the output circuits is primarily constructed by bipolar transistors.

Bipolar transistor MOS transistor hybrid semiconductor integrated

Gate circuit of combined field-effect and bipolar transistors with an

In a program control apparatus with a program ROM which forms sequence control signals for executing various control actions according to specified conditions, a memory circuit is provided which is activated during a particular operation mode to successively store information corresponding to the external conditions and also information on times taken by the operation sequence of the program control apparatus.

Program control apparatus incorporating a trace function

A high-speed operation, low-space consumption gate circuit structure-comprises a combination of complementary field-effect-transistors and bipolar transistors and discharge means for discharging accumulated charges from these transistors when the field-effect-transistors and bipolar transistors are turned off.

CMOS-BiCMOS gate circuit

An integrated circuit device comprises combinational circuits and sequential circuits. Each of the sequential circuits is provided with a (common) input control signal terminal for controlling the entry of main input terminal signals into the sequential circuit, a test data input/output terminal, a read/write signal terminal for controlling the transfer of the test data, and a latch circuit. The integrated circuit device is partitioned into sequential circuit groups, and combinational circuit groups used as partitioning test units, the main input/output terminal groups of which are connected with the sequential circuit groups through wiring layers. Test data are written into and read out from the sequential circuit groups under control of read/write signal lines through bus lines dedicated to testing. Thus, a higher fault-coverage ratio can be easily obtained with a smaller number of steps and a small test circuit area.

Integrated circuit device

A semiconductor integrated circuit device provided with a flip-flop circuit including gates which are connected to each other so as to form a closed loop, is disclosed. The device includes: first means for generating a first write timing signal, a second write timing signal, a diagnosis control signal and diagnostic data which are all concerned with the flip-flop circuit, when the device is diagnosed to detect a fault therein; second means connected to the output side of the flip-flop circuit for making and breaking the closed loop of the gates in accordance with the first write timing signal; third means connected to the output side of the flip-flop circuit for supplying the diagnostic data to the flip-flop circuit in accordance with the second write timing signal; and fourth means connected to the input side of the flip-flop circuit for blocking a signal applied to the input side of the flip-flop circuit, in accordance with the diagnosis control signal.

Semiconductor integrated circuit device

A semiconductor integrated circuit device is disclosed. A plurality of unit cells, each having at least a basic transistor device formed on one main surface of a semiconductor substrate, are arranged in a line to form a unit cell line. At least two of such unit cell lines are arranged adjacent to and in parallel with each other to form a basic cell line. A plurality of such basic cell lines are arranged in parallel with each other with a wiring region of a predetermined width being interleaved between adjacent basic cell lines.

An A/D converter used with an A/D conversion system in which each of input analog signals applied thereto is amplified at a gain selected depending or the level of said each signal and subjected to A/D conversion. The A/D converter is arranged to select a desired one of predetermined gain select modes concerned with the selection of gain of the amplifier. Further, the A/D converter produces a reference analog signal of a level corresponding to the selected gain select mode and compares the input analog signal with the reference analog signal, thereby determining whether or not the gain of the amplifier is to be changed.

Analog-digital converter

In an analog to digital converter of the type wherein an analog input voltage is compared, at a comparator with a known reference voltage selected based on a digital data produced from a control circuit, an updated digital data is generated based on a result of the comparison, and the above operation is repeated to perform digital conversion sequentially from higher bit to lower bit, there are provided two capacitors of capacitances at a predetermined ratio which is so determined as to reduce the number of serial resistors in a voltage generator circuit adapted to generate the reference voltage based on the digital data produced from the control circuit, and a voltage developing at a junction between the two capacitors is coupled to the input of the comparator, so that a change in voltage of the voltage generator circuit is reduced at a predetermined ratio in accordance with electric charge distributed on the two capacitors and is applied to the input of the comparator.

Analog to digital converter

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Nakaminato, Japan

Shigeo Kuboki