Fujitsu Semiconductor Limited

Renesas Electronics Corporation

Fujitsu Ten Limited

Fujitsu Corporation

Renesas Technology Corp.

Shigeo Koide

Yukio Ishikawa

Yasuyuki Umezaki

Hidetaka Ebeshu

Kaoru Noumi

Susumu Nishihashi

Yukio Fujisawa

Hiroaki Shimauchi

Tomoyuki Katou

Atsushi Fujita

Osamu Tago

Masaaki Tani

Takeshi Fuse

Takashi Sugimoto

Toshiyuki Igarashi

A gateway apparatus for performing transfer control of frame data between communication channels includes a routing map that stores ID information about the frame data and information about a communication channel that uses the ID information, and a search engine unit that routes the frame data to a transfer destination on the basis of the ID information of the frame data received and the routing map. The search engine unit does not transfer the frame data to the transfer destination when the ID information about the frame data received is ID information that is not used in the communication channel through which the frame data is received.

Gateway apparatus and data transfer control method

An error detector has a parity bit generator which generates error detection data for data strings sent from a CPU I/F to a memory, a parity checker which detects an error in the data strings output from the memory based on the error detection data, and a selector circuit which switchingly outputs the data from the parity bit generator and the data from a CPU which sends diagnostic data. While the selector circuit is switched to output the data from the CPU, based on the error detection data output from the selector circuit, the error detector conducts a failure diagnosis of error detection functions including at least one of the parity bit generator and the parity checker.

Error detector and error detection method

A gateway apparatus for performing transfer control of frame data between a plurality of different communication channels is provided with a time stamp unit for adding time stamp information to received frame data and a data discarding unit for determining processing delay of the frame data or abnormality of the apparatus by referring to the time stamp information and for deleting the time stamp information added to the frame data at the time of sending the frame data.

Gateway apparatus and data managing method

A clock signal generator circuit has a clock generator for generating clock signals to be supplied to a central processing unit and to functional blocks, and clock selectors. The clock generator divides the frequency of a source clock signal, to form a clock signal having an optional period. Namely, the clock generator suppresses at least one active or inactive state of the source clock signal, to generate a clock signal whose period is an integer multiple of that of the source clock signal. The clock selectors receive the clock signals generated by the clock generator and selectively supply them to the CPU and functional blocks. The clock signal generator circuit is capable of operating a microcontroller system at a required minimum speed, to optimize the power consumption of the system.

Clock signal generator circuit using a logical result of an output of a

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Kawasaki, Japan

Shigeo Koide