Renesas Electronics Corporation

Shigenori Yamashita

Junko Konishi

Toshiharu Miwa

Hidekimi Fudo

Toshihide Kawachi

Takeshi Tashiro

In an exposure process forming a predetermined circuit pattern of a semiconductor device on a wafer, a resist dimension of the resist pattern formed on a wafer and a focus position in the exposure process at a past time are measured. A resist dimension and a focus position of a wafer to which the exposure process is secondly performed are estimated by using measurement results of the measured resist dimension and focus position, and a focus offset value is calculated by using estimated values of the estimated resist dimension and focus position. Then, an exposure dose is calculated with considering this focus offset value, and a resist pattern is formed on the wafer to which the exposure process is performed by using the calculated exposure dose and focus offset value.

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Itami, Japan

Shigenori Yamashita