International Business Machines Corporation

Shigenori Shimizu

Yasunao Katayama

Nobuyuki Ohba

Moriyoshi Ohara

Hiroki Murata

Nobuyuki Oba

Atsushi Moriwaki

The present invention provides a memory system that optimizes, during a sleep mode, a refresh period for a memory device, such as DRAM, which stores meaningful data and for which a refresh operation is required to prevent the loss of data. More particularly, the present invention is directed to an apparatus for controlling, in a sleep mode, a refresh period for a memory device,that requires a refresh operation, comprises: an encoding circuit,for encoding data to obtain code that can be used to correct errors equal to or more than dual errors; a decoding circuit,for correcting errors and for decoding the corrected code; and a refresh period controller,for, following a transition to the sleep mode, changing a refresh period by using data, which is stored in the memory device,and encoded by the encoding circuit,, until the refresh period becomes longest in a condition where there is no error that can not be corrected by the decoding circuit,and the number of correctable errors does not exceed a predetermined count, and where a refresh execution circuit,for performing the refresh operation for the memory device can deal with the changed refresh period, and for, following the first end of the change of the refresh period, setting the refresh execution circuit,so that the refresh of the memory device,is performed at the refresh period at the first end of the change of the refresh period.

Refresh period control apparatus and method, and computer

The computer system comprises a processor 1, a cache memory 2 of this processor, a main memory 4, an I/O device 6 directly accessible to this main memory, an I/O controller 7, and the like. It is made so that the I/O controller can execute processing to retain data consistency between the cache memory and the main memory during access to the main memory by the I/O device. The I/O controller has an address buffer 9 that retains the cache line address of the previous access by the I/O device and it is made so that the consistency maintenance operation is not executed in cases other than the first access when accesses to the main memory by the I/O device are made continuously in the same data block.

Direct I/O control system with processor, main memory, and cache

The bandwidth of the data transfer among a main memory and snoopy caches is improved by solving the bus bottleneck in a multiprocessor system using a snoopy cache technique. Shared bus coupling is employed for an address/command bus requiring bus snoop whereas multiple data paths coupled by an interconnection network are used for the data bus not requiring bus snoop. The multiple data paths reflect the order of the snoopy operations on the order of data transfer such as to maintain data consistency among the caches.

Multiprocessor system and data transmission apparatus thereof

A cache coherency system and method which switches the data consistency maintenance protocol used for a given piece of shared data at each private cache, automatically depending upon the likelihood or frequency that the processor having the private cache concerned will accesses the given piece of shared data, and the likelihood or frequency that the other processors in a multiprocessor system will access the given piece of shared data. In the preferred embodiment, the present system and method switches between protocols of the invalidate and update types. When the processor corresponding to the private cache concerned is more likely to access the shared data concerned, it is uses the protocol of the update type because it increases the cache hit ratio. On the other hand, while other processors in the system are more likely to access the shared data concerned, it uses the protocol of the invalidate type because it reduces bus traffic required for updating the shared data. In an exemplary configuration, for each piece of shared data in each private cache, the frequency at which the processor corresponding to the private cache concerned accesses the shared data is determined. Further the frequency at which the other processors in the system modify the shared data concerned is determined. The difference between the above frequencies is calculated and compared with a predetermined reference value. The result of the comparing is used to automatically switch the protocols used for the shared data concerned at the private cache concerned.

Multiprocessor system

A cache coherency mechanism enabling efficient and dynamic switching between the maintenance protocols of the invalidate and update types. The mechanism can reduce traffic on the shared bus and improve the system performance. Usually each processor repeatedly accesses a limited area of the memory within a short span of time. That area is referred to as a 'working set' with respect to the processor. Each time a write operation occurs to shared data, each of the sharing processors determines whether or not the data belongs to its working set. If a sharing processor determines that the data belongs to its working set, then the cache consistency is maintained by the update type of procedure. Otherwise cache consistency is maintained via the invalidate type of procedure. In one embodiment the invention improves the system performance by utilizing the above mechanism for determining the working set in conjunction with a new cache protocol, ALL.sub.-- READ. A plurality of processors in a multiprocessor system using snoopy caches frequently share data or instruction code at one address. According to the ALL.sub.-- READ protocol when a processor causes a read miss for data or code at an address, other processors likely to use the data or code automatically read it into their caches. By using the working set determination mechanism, only data in the working set is applied with ALL.sub.-- READ. This invention thereby provides ALL.sub.-- READ efficiently, reduces bus traffic and improves the system performance.

Method and apparatus to maintain cache coherency in a multiprocessor

A data processing system that includes a plurality of processors with at least a portion of this plurality of processors each individually connected to a cache memory for storing data for that processor. Each cache memory includes a cache controller that is connected to a bus. Each controller includes a circuit for independently storing a data coherency procedure indicator indicating that the controller will perform one of two or more data coherency procedures. According to one procedure, when data is updated in a cache memory, corresponding data is updated in another cache that stores the corresponding data. In a second data coherency procedure, when data is updated in one cache, the corresponding data stored in another cache is invalidated. The individual and independent storing of the coherency procedure indicator enables each cache to perform either one or the other data coherency procedure without interfering with the data coherency procedures performed by other caches in the data processing system. Furthermore, the cache that is updating data provides an updating signal on the bus, which is received by the other caches on the bus. The controllers of those caches will then either update or invalidate any corresponding data in accordance with those caches stored coherency procedure indicators.

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Kawasaki, Japan

Shigenori Shimizu