Mitsubishi Denki Kabushiki Kaisha

Renesas Electronics Corporation

Renesas Technology Corp.

Mitsubushi Denki Kabushiki Kaisha

Shigenori Miyauchi

Atsuo Yamaguchi

Hirokazu Tsuruta

Seishiro Nagano

To shorten a processing time at boot time without lowering a security level, an acquiring unit acquires a public key, a signature generated with a secret key corresponding to the public key, and a program associated with the signature. A signature verification unit performs signature verification by using the public key and the signature acquired by the acquiring unit, before the program acquired by the acquiring unit is booted. A calculation unit calculates a first MAC value by using a device eigenvalue and stores the first MAC value, when the result of signature verification by the signature verification unit is appropriate. A boot unit calculates a second MAC value by using the device eigenvalue, compares the second MAC value and the stored first MAC value with each other to determine that the program is legitimate, and executes boot based on the determination result.

Semiconductor device, boot method, and boot program

A data processing apparatus is provided, which detects falsification of software to data and rewriting of the data. The data processing apparatus according to an embodiment of the present invention comprises a security unit which has an encryption circuit for decrypting an encrypted signal including secrecy data. The security unit includes a compression circuit which compresses an access signal used in accessing the security unit and outputs the compression result, and a comparison circuit which compares the compression result outputted from the compression circuit with a previously-calculated expectation value of the compression result of the access signal.

Data processing apparatus

An encoding/decoding operation portion includes an encoding/decoding operation circuit and an avoiding path for detouring the encoding decoding operation circuit and can select between encoding or decoding input data in the encoding/decoding operation circuit and detouring the encoding/decoding operation circuit to output the input data without change. Only one wire has to be provided from a selector to a key storage portion and an initialization-vector storage portion. With this construction, it is possible to realize an encoding/decoding circuit which can suppress an increase in the number of wires used to transmit a content of key data to the key storage portion and the initialization-vector storage portion and does not cause complication of circuit layout.

Encoding/decoding circuit

An addition and subtraction circuit performs addition and subtraction using a carry-in signal from another operation circuit, and outputs a carry-out signal generated through addition and subtraction to another operation circuit. A right-shift circuit performs right-shift using a shift-in signal from another operation circuit, and outputs a shift-out signal generated through right-shift to another operation circuit. Therefore, even if a data length of operation data is extended, a propagation path for a carry can be shortened, and an operation clock frequency of an encryption circuit can be increased.

Encryption circuit achieving higher operation speed

A microcomputer and memory control method for the same can reduce the number of parts, cost, and the total surface area required to mount the parts, and thus miniaturize the device in which the microcomputer is incorporated. A microcomputer with a CPU and memory storing a program executed by the CPU comprises a block access nonvolatile memory for storing the program; at least one random access memory unit for temporarily storing an externally input program; and reads the program stored in the block access nonvolatile memory and stores the program in the random access memory as a program sequentially read and executed by the CPU.

Microcomputer with efficient program storage

A semiconductor memory unit which includes a plurality of nonvolatile memories for storing data and is operable at a plurality of source voltages, comprising: a voltage detector for detecting an input voltage inputted to the semiconductor memory unit from the source voltages; and a central processing unit (CPU) which sets a maximum permissible current consumption value of the semiconductor memory unit on the basis of the input voltage and controls the number of the nonvolatile memories operated at a time such that a current consumption value of the semiconductor memory unit does not exceed the maximum permissible current consumption value.

Semiconductor memory unit in which power consumption can be restricted

A semiconductor storage device comprises a flash memory and manages the sectors in the unit of groups each consisting of n sectors. A logical sector number is converted to a logical group number and an offset address, and a conversion table is provided to convert a logical group number to a physical group number. A logical sector number is divided with n to get a quotient and a remainder which are set as a logical group number and as an offset address. An access controller determines a physical group number corresponding to the logical group number with reference to the address conversion table, and it accesses a sector in correspondence to the offset address in the physical group number. Further, a group management information for each group is stored in a memory, and when a sector of a logical sector number is accessed, a physical group number of a group storing the data of the sector is traced by referring the conversion table and the group management information.

Semiconductor storage device for group management of data sectors

A RAM ( ) used by the CPU comprises a work buffer ( ) and a work register ( ) for pipelined processing. The work buffer ( ) consists of the first to fourth work buffers ( to ) each of which stores information on predetermined data, e.g., a current processing on the data. When the CPU accesses the first to fourth work buffers ( to ), an address decoder performs an address conversion on the basis of a value (R ) of the work register ( ). For example, when the value (R ) of the work register ( ) is &ldquo;1&rdquo;, addresses (P , P , P and P ) in an address space are converted (mapped) to addresses (AD , AD , AD and AD ) of work buffers ( and ). With this constitution, in performing a plurality of data processings in parallel, the CPU can improve its operation efficiency while controlling a currently performed processing on each data.

Data processing control device

A semiconductor storage device having a plurality of block-erase type non volatile memory chips classifies the memory chips into memory groups of a number equal to twice the number of buffer memories provided in the storage device and assigns logic sector addresses sequentially to sectors contained in one erase block of each memory group in such a manner that the logic sector addresses are sequenced in series to those in the corresponding erase block of the next succeeding memory group.

Block-erase type semiconductor storage device with independent memory groups having sequential logical addresses

When the number of times erasure is performed in a first erase block in which data is to be written exceeds a predetermined number of times, a second erase block is determined for replacing data in the first erase block with data in the second erase block, and the erase number (the number of times erasure is performed) stored in the second erase block is read into a buffer. If the erase number read into the buffer is less than a certain value, data stored in the second erase block is read into the buffer. The number of the second erase block is stored in a first offset of a sub address conversion table read into a work buffer, and the number of the first erase block is stored in a second offset to replace data in the first and second erase blocks with each other.

Block erase type nonvolatile semiconductor memory device

A semiconductor storage device connectable to a host information processing apparatus having a flash memory section that stores data in sectors and wherein the flash memory section includes an address management table that stores information about the relation between logical sector numbers for data management in a host information processing apparatus and physical sector numbers for data management in the flash memory section. The flash memory section also includes a table state map that stores information about the physical locations at which the sector number information in the address management tables is stored. The semiconductor storage device also includes a flash memory control circuit for controlling data write and data read processing for the flash memory section. The control circuit refers to the table state map when the host information processing apparatus requests data write or data read to identify the physical location at which the corresponding address relation information is stored and converts the logical sector number received from the host information processing apparatus into a physical sector number based on the value stored at the identified location in the address management tables.

Semiconductor storage device utilizing address management tables and

A memory card with block erasure-type nonvolatile memory units is connected to a host apparatus by an I/O interface. The memory includes a plurality of block-erasure type nonvolatile memory units, a control circuit for inputting/outputting data to the host apparatus and managing nonvolatile memory units and address data to the memory, and a programmable logic device which converts address data to select respective erasure blocks of nonvolatile memories in accordance with a program. The control circuit programs the programmable logic device so that the address data for selecting defective erasure blocks is converted to address data for selecting other usable erasure blocks.

Memory card having block erasure type memory units which are used even

The storage device of the present invention comprises: an interface circuit, a memory comprising a plurality of block-erase type, nonvolatile memories, a control circuit for managing and controlling the memory, and an address conversion table. The control circuit searches for an erase block with an empty area and issues a command signal to the memory to cause the memory to apply voltage pulses to the selected erase block. The memory checks to determine whether or not the erase operation has been completed every time the voltage pulse is applied to the erase block, and if the erase operation has not been completed, the control unit issues another command signal to cause the memory to apply another voltage pulse to the erase block and thus determines the level of degradation of the erase characteristic of the erase block based on the number of voltage pulses applied to that erase block.

Growing community of inventors

Tokyo, Japan

Shigenori Miyauchi