Fujitsu Corporation

Fujitsu Semiconductor Limited

Shigenori Ichinose

Kenichi Ushiyama

Tetsu Tanizawa

Takehito Doi

Toru Osajima

Hideo Tokuda

Kenji Suzuki

Kenji Kumagai

Tetsuo Kawano

Noboru Yokota

Toshikatsu Hosono

Takashi Yoneda

Hideto Fukuda

Satoru Yoshikawa

Takashi Iida

Toshiaki Sugioka

Shuji Tanahashi

Masashi Takase

Kouji Banno

Sachi Kuroda

Katuzi Hirochi

Takafumi Miyahara

A design support method executed by a computer includes: detecting a layout position of a first terminal in a cell as a first layout position from layout data including a cell of a macro which is arranged at a plurality of orientations, the first terminal being arranged at a first orientation; calculating a second layout position of a first terminal which is arranged at a second orientation which is different from the first orientation based on a variation from the first orientation to the second orientation and the first layout position; associating the second layout position with the first layout position and the layout data; and outputting an association result.

Apparatus and method for design support using layout positions of first and second terminals

The method of designing a semiconductor integrated circuit of the embodiment is characterized in: reading from a memory unit a fundamental property value of a cell constituting a semiconductor integrated circuit in a case in which a variation of a property value is not taken into consideration, and reading from a memory unit variation coefficients of the property value of the cell corresponding to a dimension of a transistor constituting the cell; and performing a static timing analysis on the semiconductor integrated circuit by using the read variation coefficients and fundamental property value.

Method and program for designing semiconductor integrated circuit

A semiconductor integrated circuit includes a shielded wire line and a shielding wire line provided for the shielded wire line and divided into a plurality of segments in a longitudinal direction of the shielded wire line.

Method for determining a length of shielding of a semiconductor integrated circuit wiring

A semiconductor integrated circuit, includes a shielded wire line and a shielding wire line provided for the shielded wire line and divided into a plurality of segments in a longitudinal direction of the shielded wire line.

Semiconductor integrated circuit having reduced cross-talk noise

OCV coefficients in a path being an analysis target according to the number of gate stages are calculated in a coefficient arithmetically operating unit by canceling off a variation in delay in each gate in accordance with the number of gate stages in the target path, and timing analysis of the target path is performed in a timing analysis unit by using the OCV coefficient with the number of gate stages being considered, whereby a variation degree in the entire path is reduced in accordance with the number of gate stages in the target path, thus making it possible to carry out accurate timing analysis in consideration of the variation in a chip of a semiconductor integrated circuit.

Semiconductor integrated circuit timing analysis apparatus timing analysis method and timing analysis program

After automatic cell placement, the following steps are performed before performing automatic inter-cell routing. (S) Estimated wires having Manhattan-length path are connected between same-node terminals of cells, and detected and counted is a crosstalk error that parallel-wire length is more than a predetermined value. (S) The detected error is resolved by moving cells closely spaced less than a predetermined interval apart and connected to the error-detected estimated wires; the cell movement data is stored in a storage device; and such processes are repeated N times; and the cell placement data is modified on the basis of the cell movement data corresponding to the minimum value of error-count values of all the N times. (S) If the minimum value is not 0, (S) a buffer cell is inserted in the error-detected estimated wire. (S) Obtained is the wire density of estimated wiring having Manhattan-length path, and if the density is more than a predetermined value, the design-target frame is enlarged in size, and the process returns to the automatic cell placement process.

Method, apparatus and program product for automatic placement and routing of integrated circuit

A design support apparatus for semiconductor devices that is used to quickly arrange a non-logic cell for reducing electromagnetic radiation from a semiconductor device at the time of designing it. In this design support apparatus for semiconductor devices, a layout section does a layout for logic cells and wiring patterns to connect the logic cells. An arranged site detecting section detects an arranged site, being a site which contains neither the logic cells nor a prohibited area, after a layout is done by the layout section. A non-logic cell pattern store section stores non-logic cell patterns. A prohibited area containing site detecting section detects a prohibited area containing site, being a site which only contains a prohibited area. A non-logic cell arranging section arranges non-logic cells on the arranged site. Furthermore, the non-logic cell arranging section compares the arrangement of the prohibited area on the prohibited area containing site with a non-logic cell pattern and arranges non-logic cells only on a site where these do not conflict with each other.

Design support apparatus for semiconductor devices

A semiconductor integrated circuit includes a semiconductor chip; an inner cell region; a plurality of input/output cell regions which are located around the inner cell region, and a plurality of pads which are provided between the plurality of input/output regions and sides of the semiconductor chip. Each unit area of the plurality of input/output cell regions is assigned to a corresponding input/output cell so as to be just sufficient for the corresponding input/output cell.

Semiconductor integrated circuit and method for making wiring layout of

A semiconductor integrated circuit includes a substrate which has a predetermined width in a first direction and a predetermined length in a second direction which is approximately perpendicular to the first direction, a plurality of cells which are provided on the substrate and are grouped into a plurality of generally rectangular unit blocks, where each of the unit blocks are made up of cells having mutually different widths in the first direction but a common length in the second direction, first interconnections for supplying at least one power source voltage to the cells, where the first interconnections are provided independently for each unit block so as to supply the power source voltage in common to each of the cells making up the unit block, a row of first terminals of the cells, within each unit block, arranged in the first direction, a row of second terminals of the cells, within each unit block, arranged in the first direction an interconnection region at least including a region which is defined by the rows of the first and second terminals, and second interconnections which are provided within the interconnection region with respect to each unit block and connects the cells within the unit block.

Semiconductor integrated circuit having polycell structure and method of

A semiconductor integrated circuit comprises a plurality of first hierarchical units of logic devices each including a plurality of bipolar logic devices having a polycell structure. The bipolar logic devices have a first standardized size in a first direction and are arranged in a second direction for a second standardized size in each first hierarchical unit. Each of the first hierarchical units is defined by first and second main edges extending in the second direction for the second standardized size, and first and second side edges extending in the first direction for the first standardized size. Each of the first hierarchical units consumes a generally identical electric power and has a first power feed system extending in the second direction for the second standardized size for feeding the electric power to the bipolar logic devices therein. At least a part of the first hierarchical units are arranged in the first direction to form a plurality of second hierarchical units having respective lengths in the first direction wherein the first and second side edges are aligned in the first direction in each of the second hierarchical units. Further, the second hierarchical units are disposed such that there are at least two second hierarchical units having respective positions which are different in the second direction. Furthermore, there is provided a second power feed system extending in the first direction so as to cross the first power feed system for feeding the electric power thereto.

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Kawasaki, Japan

Shigenori Ichinose